[TableGen] Add EncoderMethod to RegisterOperand

[SamWot]

Summary

Currently custom encoding method can only be specified in Operand class. For other types of operands only way to change encoding is through general MCCodeEmitter::getMachineOpValue().
This change simplifies encoding process for complex register operands.

[vpykhtin]

LGTM.

include/llvm/Target/Target.td

 class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
   : DAGOperand {
   // RegClass - The register class of the operand.
   RegisterClass RegClass = regclass;
   // PrintMethod - The target method to call to print register operands of
   // this type. The method normally will just use an alt-name index to look
   // up the name to print. Default to the generic printOperand().
   string PrintMethod = pm;
+
+  // EncoderMethod - The target method name to call to encode this register
+  // operand.
+  string EncoderMethod = "";
+
   // ParserMatchClass - The "match class" that operands of this type fit
   // in. Match classes are used to define the order in which instructions are
   // match, to ensure that which instructions gets matched is deterministic.
   //
   // The target specific parser must be able to classify an parsed operand into
   // a unique class, which does not partially overlap with any other classes. It
   // can match a subset of some other class, in which case the AsmOperandClass
   // should declare the other operand as one of its super classes.

test/TableGen/AsmVariant.td

 // RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s
 
-// Check that cpecifying AsmVariant works correctly
+// Check that specifying AsmVariant works correctly
 
 include "llvm/Target/Target.td"
 
 def ArchInstrInfo : InstrInfo { }
 
 def FooAsmParserVariant : AsmParserVariant {
   let Variant = 0;
   let Name = "Foo";

test/TableGen/RegisterEncoder.td

+// RUN: llvm-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s
+
+// Check that EncoderMethod for RegisterOperand is working correctly
+
+include "llvm/Target/Target.td"
+
+def ArchInstrInfo : InstrInfo { }
+
+def Arch : Target {
+  let InstructionSet = ArchInstrInfo;
+}
+
+def Reg : Register<"reg">;
+
+def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>;
+
+def RegOperand : RegisterOperand<RegClass> {
+  let EncoderMethod = "barEncoder";
+}
+
+def foo : Instruction {
+  let Size = 1;
+
+  let OutOperandList = (outs);
+  let InOperandList = (ins RegOperand:$bar);
+
+  bits<8> bar;
+  bits<8> Inst = bar;
+}
+
+// CHECK: case ::foo: {
+// CHECK:   op = barEncoder
+// CHECK:   Value |= op & UINT64_C(255);
+// CHECK:   break;
+// CHECK: }
 No newline at end of file

utils/TableGen/CodeGenInstruction.cpp

for (unsigned i = 0; i != e; ++i){
     std::string OperandType = "OPERAND_UNKNOWN";
     std::string OperandNamespace = "MCOI";
     unsigned NumOps = 1;
     DagInit *MIOpInfo = nullptr;
     if (Rec->isSubClassOf("RegisterOperand")) {
       PrintMethod = Rec->getValueAsString("PrintMethod");
       OperandType = Rec->getValueAsString("OperandType");
       OperandNamespace = Rec->getValueAsString("OperandNamespace");
+      EncoderMethod = Rec->getValueAsString("EncoderMethod");
     } else if (Rec->isSubClassOf("Operand")) {
       PrintMethod = Rec->getValueAsString("PrintMethod");
       OperandType = Rec->getValueAsString("OperandType");
       OperandNamespace = Rec->getValueAsString("OperandNamespace");
       // If there is an explicit encoder method, use it.
       EncoderMethod = Rec->getValueAsString("EncoderMethod");
       MIOpInfo = Rec->getValueAsDag("MIOperandInfo");