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default tied output register
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Authored by MikeStump on Apr 24 2017, 5:42 PM.

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Reviewers
stoklund
Summary

This implements default tied output registers.

Diff Detail

Repository
rL LLVM

Event Timeline

MikeStump created this revision.Apr 24 2017, 5:42 PM
Herald added a project: Restricted Project. ยท View Herald TranscriptDec 20 2019, 4:20 PM
arsenm added a subscriber: arsenm.Feb 6 2020, 7:35 AM

It's not obvious to me what this accomplishes, and needs tests

What this accomplishes is listed in the summary and isn't meant to be opaque. https://reviews.llvm.org/D35998 in theory has a way to see it work, you can ask them for an in tree test case.

I have a port that requires default tied output registers to work. Requiring the submission of a port to bug fix an existing feature isn't the right path forward.

I have rather trivial little instructions that use default tied output registers, and they're completely broken without the patch. Trivially, the original author didn't think about the easy cases, as my instructions are rather trivial. I'd like to think my patch handles even the hard cases, but, I didn't prove to myself that it is complete. I believe it is monotonically closer however.

What this accomplishes is listed in the summary and isn't meant to be opaque. https://reviews.llvm.org/D35998 in theory has a way to see it work, you can ask them for an in tree test case.

Commit message needs more elaboration. Default tied output registers already look implemented to me, and this is an asm matcher problem. The case handled here also looks implemented, so this needs an explanation for what this is fixing