[GlobalISel][X86] handle not symmetric G_COPY

[igorb]

Summary

handle not symmetric G_COPY

[guyblank]

test/CodeGen/X86/GlobalISel/binop.ll

27

can you add tests just for the COPY?
returning the arguments i suppose.

[igorb]

• add tests

[igorb]

test/CodeGen/X86/GlobalISel/binop.ll

27

I added tests for not symmetric G_COPY to callingconv.ll. Tests for just a G_COPY already exist in the same file (like test_arg_i32).

[guyblank]

LGTM

lib/Target/X86/X86InstructionSelector.cpp

static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
   unsigned DstReg = I.getOperand(0).getReg();
   if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
     assert(I.isCopy() && "Generic operators do not allow physical registers");
     return true;
   }
 
   const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
   const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
-  (void)DstSize;
   unsigned SrcReg = I.getOperand(1).getReg();
   const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
-  (void)SrcSize;
+
   assert((!TargetRegisterInfo::isPhysicalRegister(SrcReg) || I.isCopy()) &&
          "No phys reg on generic operators");
   assert((DstSize == SrcSize ||
           // Copies are a mean to setup initial types, the number of
           // bits may not exactly match.
           (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
            DstSize <= RBI.getSizeInBits(SrcReg, MRI, TRI))) &&
          "Copy with different width?!");
 
   const TargetRegisterClass *RC = nullptr;
 
   switch (RegBank.getID()) {
   case X86::GPRRegBankID:
     assert((DstSize <= 64) && "GPRs cannot get more than 64-bit width values.");
     RC = getRegClassForTypeOnBank(MRI.getType(DstReg), RegBank);
+
+    // Change the physical register
+    if (SrcSize > DstSize && TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
+      if (RC == &X86::GR32RegClass)
+        I.getOperand(1).setSubReg(X86::sub_32bit);
+      else if (RC == &X86::GR16RegClass)
+        I.getOperand(1).setSubReg(X86::sub_16bit);
+      else if (RC == &X86::GR8RegClass)
+        I.getOperand(1).setSubReg(X86::sub_8bit);
+
+      I.getOperand(1).substPhysReg(SrcReg, TRI);
+    }
     break;
   case X86::VECRRegBankID:
     RC = getRegClassForTypeOnBank(MRI.getType(DstReg), RegBank);
     break;
   default:
     llvm_unreachable("Unknown RegBank!");
   }
 

test/CodeGen/X86/GlobalISel/binop.ll

 ; ALL-NEXT:    # kill: %EDI<def> %EDI<kill> %RDI<def>
 ; ALL-NEXT:    # kill: %ESI<def> %ESI<kill> %RSI<def>
 ; ALL-NEXT:    leal (%rsi,%rdi), %eax
 ; ALL-NEXT:    retq
   %ret = add i32 %arg1, %arg2
   ret i32 %ret
 }
 
+define i16 @test_add_i16(i16 %arg1, i16 %arg2) {
+; ALL-LABEL: test_add_i16:
+; ALL:       # BB#0:
+; ALL-NEXT:    # kill: %DI<def> %DI<kill> %RDI<def>
+; ALL-NEXT:    # kill: %SI<def> %SI<kill> %RSI<def>
+; ALL-NEXT:    leal (%rsi,%rdi), %eax
+; ALL-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
+; ALL-NEXT:    retq
+  %ret = add i16 %arg1, %arg2
+  ret i16 %ret
+}
+
+define i8 @test_add_i8(i8 %arg1, i8 %arg2) {
+; ALL-LABEL: test_add_i8:
+; ALL:       # BB#0:
+; ALL-NEXT:    addb %dil, %sil
+; ALL-NEXT:    movl %esi, %eax
+; ALL-NEXT:    retq
+  %ret = add i8 %arg1, %arg2
+  ret i8 %ret
+}
+
 define i64 @test_sub_i64(i64 %arg1, i64 %arg2) {
 ; ALL-LABEL: test_sub_i64:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    subq %rsi, %rdi
 ; ALL-NEXT:    movq %rdi, %rax
 ; ALL-NEXT:    retq
   %ret = sub i64 %arg1, %arg2
   ret i64 %ret

test/CodeGen/X86/GlobalISel/select-add.mir

 # RUN: llc -mtriple=x86_64-linux-gnu                                  -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE
 # RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx                      -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX
 # RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f                  -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F
 # RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL
 
 --- |
   define i64 @test_add_i64(i64 %arg1, i64 %arg2) {
     %ret = add i64 %arg1, %arg2
     ret i64 %ret
   }
 
   define i32 @test_add_i32(i32 %arg1, i32 %arg2) {
     %ret = add i32 %arg1, %arg2
     ret i32 %ret
   }
 
+  define i16 @test_add_i16(i16 %arg1, i16 %arg2) {
+    %ret = add i16 %arg1, %arg2
+    ret i16 %ret
+  }
+
+  define i8 @test_add_i8(i8 %arg1, i8 %arg2) {
+    %ret = add i8 %arg1, %arg2
+    ret i8 %ret
+  }
+
   define float @test_add_float(float %arg1, float %arg2) {
     %ret = fadd float %arg1, %arg2
     ret float %ret
   }
 
   define double @test_add_double(double %arg1, double %arg2) {
     %ret = fadd double %arg1, %arg2
     ret double %ret
   }
 
   define <4 x i32> @test_add_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {
     %ret = add <4 x i32> %arg1, %arg2
     ret <4 x i32> %ret
   }
 
   define <4 x float>  @test_add_v4f32(<4 x float> %arg1, <4 x float>  %arg2) {
     %ret = fadd <4 x float>  %arg1, %arg2
     ret <4 x float>  %ret
   }
 ...
 
 ---
 name:            test_add_i64
+# ALL-LABEL: name:            test_add_i64
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
 # ALL-NEXT:  - { id: 0, class: gr64 }
 # ALL-NEXT:  - { id: 1, class: gr64 }
 # ALL-NEXT:  - { id: 2, class: gr64 }
 registers:
   - { id: 0, class: gpr }
bb.1 (%ir-block.0):
     %1(s64) = COPY %rsi
     %2(s64) = G_ADD %0, %1
     %rax = COPY %2(s64)
 
 ...
 
 ---
 name:            test_add_i32
+# ALL-LABEL: name:            test_add_i32
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
 # ALL-NEXT:  - { id: 0, class: gr32 }
 # ALL-NEXT:  - { id: 1, class: gr32 }
 # ALL-NEXT:  - { id: 2, class: gr32 }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:      %0 = COPY %edi
 # ALL-NEXT: %1 = COPY %esi
 # ALL-NEXT: %2 = ADD32rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %esi
 
     %0(s32) = COPY %edi
     %1(s32) = COPY %esi
     %2(s32) = G_ADD %0, %1
     %rax = COPY %2(s32)
 
 ...
 ---
+name:            test_add_i16
+# ALL-LABEL: name:            test_add_i16
+alignment:       4
+legalized:       true
+regBankSelected: true
+selected:        false
+# ALL:      registers:
+# ALL-NEXT:  - { id: 0, class: gr16 }
+# ALL-NEXT:  - { id: 1, class: gr16 }
+# ALL-NEXT:  - { id: 2, class: gr16 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+# ALL: %0 = COPY %di
+# ALL: %1 = COPY %si
+# ALL: %2 = ADD16rr %0, %1, implicit-def %eflags
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi, %esi
+
+    %0(s16) = COPY %edi
+    %1(s16) = COPY %esi
+    %2(s16) = G_ADD %0, %1
+    %ax = COPY %2(s16)
+    RET 0, implicit %ax
+
+...
+---
+name:            test_add_i8
+# ALL-LABEL: name:            test_add_i8
+alignment:       4
+legalized:       true
+regBankSelected: true
+selected:        false
+# ALL:      registers:
+# ALL-NEXT:  - { id: 0, class: gr8 }
+# ALL-NEXT:  - { id: 1, class: gr8 }
+# ALL-NEXT:  - { id: 2, class: gr8 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+# ALL: %0 = COPY %dil
+# ALL: %1 = COPY %sil
+# ALL: %2 = ADD8rr %0, %1, implicit-def %eflags
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi, %esi
+
+    %0(s8) = COPY %edi
+    %1(s8) = COPY %esi
+    %2(s8) = G_ADD %0, %1
+    %al = COPY %2(s8)
+    RET 0, implicit %al
+
+...
+---
 name:            test_add_float
+# ALL-LABEL: name:            test_add_float
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
 # ALL: registers:
 # NO_AVX512F-NEXT:  - { id: 0, class: fr32 }
 # NO_AVX512F-NEXT:  - { id: 1, class: fr32 }
bb.1 (%ir-block.0):
     %1(s32) = COPY %xmm1
     %2(s32) = G_FADD %0, %1
     %xmm0 = COPY %2(s32)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_add_double
+# ALL-LABEL: name:            test_add_double
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
 # ALL: registers:
 # NO_AVX512F-NEXT:  - { id: 0, class: fr64 }
 # NO_AVX512F-NEXT:  - { id: 1, class: fr64 }
bb.1 (%ir-block.0):
     %1(s64) = COPY %xmm1
     %2(s64) = G_FADD %0, %1
     %xmm0 = COPY %2(s64)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_add_v4i32
+# ALL-LABEL: name:            test_add_v4i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
 # ALL: registers:
 # NO_AVX512VL-NEXT:  - { id: 0, class: vr128 }
 # NO_AVX512VL-NEXT:  - { id: 1, class: vr128 }
bb.1 (%ir-block.0):
     %1(<4 x s32>) = COPY %xmm1
     %2(<4 x s32>) = G_ADD %0, %1
     %xmm0 = COPY %2(<4 x s32>)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_add_v4f32
+# ALL-LABEL: name:            test_add_v4f32
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
 # ALL: registers:
 # NO_AVX512VL-NEXT:  - { id: 0, class: vr128 }
 # NO_AVX512VL-NEXT:  - { id: 1, class: vr128 }