[Thumb-1] Fix corner cases for compressed jump tables

[weimingz]

Summary

When synthesized TBB/TBH is expanded, we need to avoid the case of:

BaseReg is redefined after the load of branching target. E.g.:

%R2 = tLEApcrelJT <jt#1>
%R1 =  tLDRr %R1, %R2
%R2 = tLDRspi %SP, 12
tBR_JTr %R1

After JT compression, it becomes

%R2 = tLEApcrelJT <jt#1>
%R2 = tLDRspi %SP, 12
tTBB_JT %R2, %R1

[weimingz]

This fixes some SPEC2000 fails when build for Thumb1 with -Os.
I do not upload the lit test because it's not easy to reduce to a simple/clean one as it needs specific reg alloc to show the problem.

[jmolloy]

LGTM, thanks for catching these!

[weimingz]

Just find that one case was fixed by r297871 ARM: avoid clobbering register in v6 jump-table expansion.

llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp

if (isThumb2) {
         continue;
       if (Load->getOperand(1).getReg() != ShiftedIdxReg ||
           Load->getOperand(2).getReg() != BaseReg ||
           !Load->getOperand(1).isKill())
         continue;
 
       // If we're in PIC mode, there should be another ADD following.
       auto *TRI = STI->getRegisterInfo();
+
+      // %base cannot be redefined after the load as it will appear before
+      // TBB/TBH like:
+      //      %base =
+      //      %base =
+      //      tBB %base, %idx
+      if (registerDefinedBetween(BaseReg, Load->getNextNode(), MBB->end(), TRI))
+        continue;
+
       if (isPositionIndependentOrROPI) {
         MachineInstr *Add = Load->getNextNode();
         if (Add->getOpcode() != ARM::tADDrr ||
             Add->getOperand(2).getReg() != Load->getOperand(0).getReg() ||
             Add->getOperand(3).getReg() != BaseReg ||
             !Add->getOperand(2).isKill())
           continue;
         if (Add->getOperand(0).getReg() != MI->getOperand(0).getReg())