DAG: Set hasCalls on frame info earlier

[arsenm]

Summary

AMDGPU needs to know if calls are present when lowering arguments,
but this was only set later. Set it along with other stack properties.

[arsenm]

Skip intrinsics

[arsenm]

This seems to break a variety of tests in other targets. Maybe a smarter version of isLoweredToCall is needed?

[arsenm]

Make it a target hook.

There are some special cases that make it difficult to make this
test generically. SystemZ emits some libcalls as special instructions,
and this depends on whether the target will end up emitting a
tail call.

[arsenm]

ping

[arsenm]

I found a better solution which avoids needing to predict this from a call

include/llvm/Target/TargetLowering.h

public:
 
   /// Return true if the target may be able emit the call instruction as a tail
   /// call. This is used by optimization passes to determine if it's profitable
   /// to duplicate return instructions to enable tailcall optimization.
   virtual bool mayBeEmittedAsTailCall(CallInst *) const {
     return false;
   }
 
+  /// Return true if it should be assumed this will be emitted as a call, not a
+  /// tail call or special instruction.
+  virtual bool shouldAssumeEmittedAsCall(ImmutableCallSite CS) const {
+    return false;
+  }
+
   /// Return the builtin name for the __builtin___clear_cache intrinsic
   /// Default is to invoke the clear cache library call
   virtual const char * getClearCacheBuiltinName() const {
     return "__clear_cache";
   }
 
   /// Return the register ID of the name passed in. Used by named register
   /// global variables extension. There is no target-independent behaviour

lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

for (const Instruction &I : BB) {
               TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
               std::pair<unsigned, const TargetRegisterClass *> PhysReg =
                   TLI->getRegForInlineAsmConstraint(TRI, Op.ConstraintCode,
                                                     Op.ConstraintVT);
               if (PhysReg.first == SP)
                 MF->getFrameInfo().setHasOpaqueSPAdjustment(true);
             }
           }
+        } else if (TLI->shouldAssumeEmittedAsCall(CS)) {
+          MF->getFrameInfo().setHasCalls(true);
         }
       }
 
       // Look for calls to the @llvm.va_start intrinsic. We can omit some
       // prologue boilerplate for variadic functions that don't examine their
       // arguments.
       if (const auto *II = dyn_cast<IntrinsicInst>(&I)) {
         if (II->getIntrinsicID() == Intrinsic::vastart)

lib/Target/AMDGPU/SIISelLowering.h

class SITargetLowering final : public AMDGPUTargetLowering {
   /// global value \p GV, false otherwise.
   bool shouldEmitPCReloc(const GlobalValue *GV) const;
 
 public:
   SITargetLowering(const TargetMachine &tm, const SISubtarget &STI);
 
   const SISubtarget *getSubtarget() const;
 
+  bool shouldAssumeEmittedAsCall(ImmutableCallSite CS) const override;
+
   bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
                           EVT /*VT*/) const override;
 
   bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
                           unsigned IntrinsicID) const override;
 
   bool getAddrModeArguments(IntrinsicInst * /*I*/,
                             SmallVectorImpl<Value*> &/*Ops*/,

lib/Target/AMDGPU/SIISelLowering.cpp

 const SISubtarget *SITargetLowering::getSubtarget() const {
   return static_cast<const SISubtarget *>(Subtarget);
 }
 
 //===----------------------------------------------------------------------===//
 // TargetLowering queries
 //===----------------------------------------------------------------------===//
 
+bool SITargetLowering::shouldAssumeEmittedAsCall(ImmutableCallSite CS) const {
+  const Function *F = CS.getCalledFunction();
+  return !F || !F->isIntrinsic();
+}
+
 bool SITargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &,
                                           EVT) const {
   // SI has some legal vector types, but no legal vector operations. Say no
   // shuffles are legal in order to prefer scalarizing some vector operations.
   return false;
 }
 
 bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,