[ARM] Prefer BIC over BFC in ARM mode.

[efriedma]

Summary

BIC is generally faster, and it can put the output in a different register from the input.

We already do this in Thumb2 mode; not sure why the equivalent fix never got applied to ARM mode.

llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

def  MVNi  : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
   bits<4> Rd;
   bits<12> imm;
   let Inst{25} = 1;
   let Inst{19-16} = 0b0000;
   let Inst{15-12} = Rd;
   let Inst{11-0} = imm;
 }
 
+let AddedComplexity = 1 in
 def : ARMPat<(and   GPR:$src, mod_imm_not:$imm),
              (BICri GPR:$src, mod_imm_not:$imm)>;
 
 //===----------------------------------------------------------------------===//
 //  Multiply Instructions.
 //
 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
              string opc, string asm, list<dag> pattern>

llvm/trunk/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll

 ; CHECK: sub       sp, sp, #4
 ; CHECK: add       r0, sp, #4
 ; CHECK: stm       sp, {r0, r1, r2, r3}
   %g = alloca i8*
   %g1 = bitcast i8** %g to i8*
   call void @llvm.va_start(i8* %g1)
 
 ; CHECK: add  [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
-; CHECK: bfc  [[REG]], #0, #3
+; CHECK: bic  [[REG]], [[REG]], #7
   %0 = va_arg i8** %g, double
   call void @llvm.va_end(i8* %g1)
 
   ret void
 }
 
 ; CHECK-LABEL: main:
 ; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val

llvm/trunk/test/CodeGen/ARM/bfi.ll

; CHECK: bfi r0, r1, #8, #9
   %and2 = shl i32 %b, 8
   %shl = and i32 %and2, 130816
   %or = or i32 %shl, %and
   ret i32 %or
 }
 
 define i32 @f7(i32 %x, i32 %y) {
 ; CHECK-LABEL: f7:
-; CHECK: bfi r1, r0, #4, #1
+; CHECK: bfi r0, r2, #4, #1
   %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
   %and = and i32 %x, 4
   %or = or i32 %y2, 16
   %cmp = icmp ne i32 %and, 0
   %sel = select i1 %cmp, i32 %or, i32 %y2
   ret i32 %sel
 }
 
 define i32 @f8(i32 %x, i32 %y) {
 ; CHECK-LABEL: f8:
-; CHECK: bfi r1, r0, #4, #1
-; CHECK: bfi r1, r0, #5, #1
+; CHECK: bfi r0, r2, #4, #1
+; CHECK: bfi r0, r2, #5, #1
   %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
   %and = and i32 %x, 4
   %or = or i32 %y2, 48
   %cmp = icmp ne i32 %and, 0
   %sel = select i1 %cmp, i32 %or, i32 %y2
   ret i32 %sel
 }
 
 define i32 @f9(i32 %x, i32 %y) {
 ; CHECK-LABEL: f9:
 ; CHECK-NOT: bfi
   %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
   %and = and i32 %x, 4
   %or = or i32 %y2, 48
   %cmp = icmp ne i32 %and, 0
   %sel = select i1 %cmp, i32 %y2, i32 %or
   ret i32 %sel
 }
 
 define i32 @f10(i32 %x, i32 %y) {
 ; CHECK-LABEL: f10:
-; CHECK: bfi r1, r0, #4, #2
+; CHECK: bfi r0, r2, #4, #2
   %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
   %and = and i32 %x, 4
   %or = or i32 %y2, 32
   %cmp = icmp ne i32 %and, 0
   %sel = select i1 %cmp, i32 %or, i32 %y2
 
   %aand = and i32 %x, 2
   %aor = or i32 %sel, 16
   %acmp = icmp ne i32 %aand, 0
   %asel = select i1 %acmp, i32 %aor, i32 %sel
 
   ret i32 %asel
 }
 
 define i32 @f11(i32 %x, i32 %y) {
 ; CHECK-LABEL: f11:
-; CHECK: bfi r1, r0, #4, #3
+; CHECK: bfi r0, r2, #4, #3
   %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
   %and = and i32 %x, 4
   %or = or i32 %y2, 32
   %cmp = icmp ne i32 %and, 0
   %sel = select i1 %cmp, i32 %or, i32 %y2
 
   %aand = and i32 %x, 2
   %aor = or i32 %sel, 16
   %acmp = icmp ne i32 %aand, 0
   %asel = select i1 %acmp, i32 %aor, i32 %sel
 
   %band = and i32 %x, 8
   %bor = or i32 %asel, 64
   %bcmp = icmp ne i32 %band, 0
   %bsel = select i1 %bcmp, i32 %bor, i32 %asel
 
   ret i32 %bsel
 }
 
 define i32 @f12(i32 %x, i32 %y) {
 ; CHECK-LABEL: f12:
-; CHECK: bfi r1, r0, #4, #1
+; CHECK: bfi r0, r2, #4, #1
   %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
   %and = and i32 %x, 4
   %or = or i32 %y2, 16
   %cmp = icmp eq i32 %and, 0
   %sel = select i1 %cmp, i32 %y2, i32 %or
   ret i32 %sel
 }
 

llvm/trunk/test/CodeGen/ARM/bic.ll

 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b) {
+; CHECK-LABEL: f1:
+; CHECK: bic  r0, r0, r1
     %tmp = xor i32 %b, 4294967295
     %tmp1 = and i32 %a, %tmp
     ret i32 %tmp1
 }
 
-; CHECK: bic  r0, r0, r1
-
 define i32 @f2(i32 %a, i32 %b) {
+; CHECK-LABEL: f2:
+; CHECK: bic  r0, r0, r1
     %tmp = xor i32 %b, 4294967295
     %tmp1 = and i32 %tmp, %a
     ret i32 %tmp1
 }
 
-; CHECK: bic  r0, r0, r1
+define i32 @f3(i32 %a) {
+; CHECK-LABEL: f3:
+; CHECK: bic r0, r0, #255
+    %tmp = and i32 %a, -256
+    ret i32 %tmp
+}

llvm/trunk/test/CodeGen/ARM/fp16-promote.ll

 }
 
 ; CHECK-FP16-LABEL: test_fabs:
 ; CHECK-FP16: vcvtb.f32.f16
 ; CHECK-FP16: vabs.f32
 ; CHECK-FP16: vcvtb.f16.f32
 ; CHECK-LIBCALL-LABEL: test_fabs:
 ; CHECK-LIBCALL: bl __aeabi_h2f
-; CHECK-LIBCALL: bfc
+; CHECK-LIBCALL: bic
 ; CHECK-LIBCALL: bl __aeabi_f2h
 define void @test_fabs(half* %p) {
   %a = load half, half* %p, align 2
   %r = call half @llvm.fabs.f16(half %a)
   store half %r, half* %p
   ret void
 }
 

 ; CHECK-FP16: vcvtb.f32.f16
 ; CHECK-FP16: vcvtb.f32.f16
 ; CHECK-FP16: vbsl
 ; CHECK-FP16: vcvtb.f16.f32
 ; CHECK-LIBCALL-LABEL: test_copysign:
 ; CHECK-LIBCALL: bl __aeabi_h2f
 ; CHECK-LIBCALL: bl __aeabi_h2f
 ; CHECK-VFP-LIBCALL: vbsl
-; CHECK-NOVFP: bfc
+; CHECK-NOVFP: bic
 ; CHECK-NOVFP: and
 ; CHECK-NOVFP: orr
 ; CHECK-LIBCALL: bl __aeabi_f2h
 define void @test_copysign(half* %p, half* %q) #0 {
   %a = load half, half* %p, align 2
   %b = load half, half* %q, align 2
   %r = call half @llvm.copysign.f16(half %a, half %b)
   store half %r, half* %p

llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll

 ; If one side is zero, the other size sign bit is masked off to allow
 ; +0.0 == -0.0
 define arm_apcscc i32 @t2(double* %a, double* %b) nounwind {
 entry:
 ; CHECK-LABEL: t2:
 ; CHECK-NOT: vldr
 ; CHECK: ldrd [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], [r0]
 ; CHECK-NOT: b LBB
-; CHECK: bfc [[REG2]], #31, #1
+; CHECK: bic [[REG2]], [[REG2]], #-2147483648
 ; CHECK: cmp [[REG1]], #0
 ; CHECK: cmpeq [[REG2]], #0
 ; CHECK-NOT: vcmp.f32
 ; CHECK-NOT: vmrs
 ; CHECK: bne
   %0 = load double, double* %a
   %1 = fcmp oeq double %0, 0.000000e+00
   br i1 %1, label %bb1, label %bb2

llvm/trunk/test/CodeGen/ARM/softfp-fabs-fneg.ll

 ; RUN: llc -mtriple=armv7 < %s | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK
 ; RUN: llc -mtriple=thumbv7 < %s | FileCheck %s --check-prefix=CHECK-THUMB --check-prefix=CHECK
 
 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
 target triple = "armv7--"
 
 define double @f(double %a) {
   ; CHECK-LABEL: f:
   ; CHECK: bfc r1, #31, #1
   ; CHECK-NEXT: bx lr
   %x = call double @llvm.fabs.f64(double %a) readnone
   ret double %x
 }
 
 define float @g(float %a) {
   ; CHECK-LABEL: g:
-  ; CHECK-THUMB: bic r0, r0, #-2147483648
-  ; CHECK-ARM: bfc r0, #31, #1
+  ; CHECK: bic r0, r0, #-2147483648
   ; CHECK-NEXT: bx lr
   %x = call float @llvm.fabs.f32(float %a) readnone
   ret float %x
 }
 
 define double @h(double %a) {
   ; CHECK-LABEL: h:
   ; CHECK: eor r1, r1, #-2147483648

llvm/trunk/test/CodeGen/ARM/va_arg.ll

 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -pre-RA-sched=source | FileCheck %s
 ; Test that we correctly align elements when using va_arg
 
 ; CHECK-LABEL: test1:
 ; CHECK-NOT: bfc
 ; CHECK: add  [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
-; CHECK: bfc  [[REG]], #0, #3
-; CHECK-NOT: bfc
+; CHECK: bic  {{(r[0-9]+)|(lr)}}, [[REG]], #7
+; CHECK-NOT: bic
 
 define i64 @test1(i32 %i, ...) nounwind optsize {
 entry:
   %g = alloca i8*, align 4
   %g1 = bitcast i8** %g to i8*
   call void @llvm.va_start(i8* %g1)
   %0 = va_arg i8** %g, i64
   call void @llvm.va_end(i8* %g1)
   ret i64 %0
 }
 
 ; CHECK-LABEL: test2:
 ; CHECK-NOT: bfc
 ; CHECK: add  [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
-; CHECK: bfc  [[REG]], #0, #3
-; CHECK-NOT:  bfc
+; CHECK: bic  {{(r[0-9]+)|(lr)}}, [[REG]], #7
+; CHECK-NOT:  bic
 ; CHECK: bx lr
 
 define double @test2(i32 %a, i32* %b, ...) nounwind optsize {
 entry:
   %ap = alloca i8*, align 4                       ; <i8**> [#uses=3]
   %ap1 = bitcast i8** %ap to i8*                  ; <i8*> [#uses=2]
   call void @llvm.va_start(i8* %ap1)
   %0 = va_arg i8** %ap, i32                       ; <i32> [#uses=0]