[SDAG] Fix visitAND optimization to deal with vector extract case again.

[niravd]

Summary

Fix case elided by rL298920.

Fixes PR32545.

[efriedma]

LGTM, I guess. We really need come up with better idioms for replacing loads in DAGCombine.

llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
     }
 
     if (B && Constant.isAllOnesValue()) {
       // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
       // preserve semantics once we get rid of the AND.
       SDValue NewLoad(Load, 0);
 
       // Fold the AND away. NewLoad may get replaced immediately.
-      CombineTo(N, NewLoad);
+      CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
 
       if (Load->getExtensionType() == ISD::EXTLOAD) {
         NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
                               Load->getValueType(0), SDLoc(Load),
                               Load->getChain(), Load->getBasePtr(),
                               Load->getOffset(), Load->getMemoryVT(),
                               Load->getMemOperand());
         // Replace uses of the EXTLOAD with the new ZEXTLOAD.

llvm/trunk/test/CodeGen/ARM/pr32545.ll

+; RUN: llc %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "armv7--linux-gnueabi"
+
+; CHECK: vld1.16  {[[DREG:d[0-9]+]][0]}, {{.*}}
+; CHECK: vmovl.u8 [[QREG:q[0-9]+]], [[DREG]]
+; CHECK: vmovl.u16  [[QREG]], [[DREG]]
+
+define void @f(i32 %dstStride, i8* %indvars.iv, <2 x i8>* %zz) {
+entry:
+  br label %for.body
+
+for.body:
+  %tmp = load <2 x i8>, <2 x i8>* %zz, align 1
+  %tmp1 = extractelement <2 x i8> %tmp, i32 0
+  %.lhs.rhs = zext i8 %tmp1 to i32
+  call void @g(i32 %.lhs.rhs)
+  br label %for.body
+}
+
+declare void @g(i32)