[X86][MMX] Add fast-isel support for MMX non-temporal writes

[craig.topper]

LGTM

llvm/trunk/lib/Target/X86/X86FastISel.cpp

 
 /// X86FastEmitStore - Emit a machine instruction to store a value Val of
 /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
 /// and a displacement offset, or a GlobalAddress,
 /// i.e. V. Return true if it is possible.
 bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill,
                                    X86AddressMode &AM,
                                    MachineMemOperand *MMO, bool Aligned) {
+  bool HasSSE1 = Subtarget->hasSSE1();
   bool HasSSE2 = Subtarget->hasSSE2();
   bool HasSSE4A = Subtarget->hasSSE4A();
   bool HasAVX = Subtarget->hasAVX();
   bool HasAVX512 = Subtarget->hasAVX512();
   bool HasVLX = Subtarget->hasVLX();
   bool IsNonTemporal = MMO && MMO->isNonTemporal();
 
   // Get opcode and regclass of the output for the given store instruction.
if (X86ScalarSSEf32) {
       if (IsNonTemporal && HasSSE4A)
         Opc = X86::MOVNTSD;
       else
         Opc = HasAVX512 ? X86::VMOVSDZmr :
               HasAVX ? X86::VMOVSDmr : X86::MOVSDmr;
     } else
       Opc = X86::ST_Fp64m;
     break;
+  case MVT::x86mmx:
+    Opc = (IsNonTemporal && HasSSE1) ? X86::MMX_MOVNTQmr : X86::MMX_MOVQ64mr;
+    break;
   case MVT::v4f32:
     if (Aligned) {
       if (IsNonTemporal)
         Opc = HasVLX ? X86::VMOVNTPSZ128mr :
               HasAVX ? X86::VMOVNTPSmr : X86::MOVNTPSmr;
       else
         Opc = HasVLX ? X86::VMOVAPSZ128mr :
               HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr;

llvm/trunk/test/CodeGen/X86/fast-isel-nontemporal.ll

 ; MMX Store
 ;
 
 define void @test_mmx(x86_mmx* nocapture %a0, x86_mmx* nocapture %a1) {
 ; ALL-LABEL: test_mmx:
 ; ALL:       # BB#0: # %entry
 ; ALL-NEXT:    movq (%rdi), %mm0
 ; ALL-NEXT:    psrlq $3, %mm0
-; ALL-NEXT:    movq %mm0, (%rsi)
+; ALL-NEXT:    movntq %mm0, (%rsi)
 ; ALL-NEXT:    retq
 entry:
   %0 = load x86_mmx, x86_mmx* %a0
   %1 = call x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx %0, i32 3)
   store x86_mmx %1, x86_mmx* %a1, align 8, !nontemporal !1
   ret void
 }
 declare x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx, i32) nounwind readnone