[CodeGen] Add a 'NoAAResultsWrapperPass', and use it in SDAG/2Addr.

[ab]

Summary

Before r247167, the pass manager builder controlled which AA
implementations were used, exporting them all in the AliasAnalysis
analysis group.

Now, AAResultsWrapperPass always uses BasicAA, but still uses other
AA implementations if made available in the pass pipeline.

IIUC, one of the many quirks of the legacy pass manager is that we
never actually recomputed BasicAA's dependencies, even though it
requires DT. I'm not sure how that never caused a problem in practice.

But regardless, both SDAG and TwoAddress are required at O0, and really
don't need to be doing fancy optimizations based on useful AA results.

Add a 'NoAAResultsWrapperPass', which just wraps an empty AAResults.
This lets us always provide conservative answers.

Ideally, the decision to use this instead of AAResultsWrapperPass
should live at a higher level, in TargetPassConfig. However, these
passes are already opt-level-aware, and untangling the legacy pass
manager to support adding arbitrary AA passes if the AAResultsWrapper
was required is a huge undertaking (and would basically undo a few
of Chandler's cleanups).

I'm really not sure this is the right approach. WDYT?

[chandlerc]

After looking at the uses of AA in both passes here, I think I like the alternative idea of making AA optional directly in the passes. Then, for the old PM, we can use something like getAnalysisIfAvailable and just not mark the analysis as required when not optimizing codegen. What do you think? Would it be helpful if I hack up a patch?

[ab]

In D31642#724540, @chandlerc wrote:

After looking at the uses of AA in both passes here, I think I like the alternative idea of making AA optional directly in the passes. Then, for the old PM, we can use something like getAnalysisIfAvailable and just not mark the analysis as required when not optimizing codegen. What do you think? Would it be helpful if I hack up a patch?

Yeah, that was my original attempt: I sent D32766.

I very slightly prefer hiding the fact that the pass is optional, but both approaches seem reasonable. Thanks for the help!

[ab]

D32766 replaced this; closing.

include/llvm/Analysis/AliasAnalysis.h

public:
 
   bool runOnFunction(Function &F) override;
 
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 };
 
 FunctionPass *createAAResultsWrapperPass();
 
+/// A wrapper pass to provide the legacy pass manager access to the empty
+/// AAResults object, that always provides conservative results.
+class NoAAResultsWrapperPass : public FunctionPass {
+  std::unique_ptr<AAResults> AAR;
+
+public:
+  static char ID;
+
+  NoAAResultsWrapperPass();
+
+  AAResults &getAAResults() { return *AAR; }
+  const AAResults &getAAResults() const { return *AAR; }
+
+  bool runOnFunction(Function &F) override;
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override;
+};
+
+FunctionPass *createNoAAResultsWrapperPass();
+
 /// A wrapper pass around a callback which can be used to populate the
 /// AAResults in the AAResultsWrapperPass from an external AA.
 ///
 /// The callback provided here will be used each time we prepare an AAResults
 /// object, and will receive a reference to the function wrapper pass, the
 /// function, and the AAResults object to populate. This should be used when
 /// setting up a custom pass pipeline to inject a hook into the AA results.
 ImmutablePass *createExternalAAWrapperPass(

include/llvm/CodeGen/Passes.h

/// MachineDominanaceFrontier - This pass is a machine dominators analysis pass.
 
   /// LiveIntervals - This analysis keeps track of the live ranges of virtual
   /// and physical registers.
   extern char &LiveIntervalsID;
 
   /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
   extern char &LiveStacksID;
 
-  /// TwoAddressInstruction - This pass reduces two-address instructions to
-  /// use two operands. This destroys SSA information but it is desired by
-  /// register allocators.
-  extern char &TwoAddressInstructionPassID;
+  /// This pass reduces two-address instructions to use two operands. This
+  /// destroys SSA information but it is desired by register allocators.
+  FunctionPass *createTwoAddressInstructionPass(bool UseAA);
 
   /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
   extern char &ProcessImplicitDefsID;
 
   /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
   extern char &RegisterCoalescerID;
 
   /// MachineScheduler - This pass schedules machine instructions.

include/llvm/InitializePasses.h

 void initializeMergeFunctionsPass(PassRegistry&);
 void initializeMergedLoadStoreMotionLegacyPassPass(PassRegistry&);
 void initializeMetaRenamerPass(PassRegistry&);
 void initializeModuleDebugInfoPrinterPass(PassRegistry&);
 void initializeModuleSummaryIndexWrapperPassPass(PassRegistry&);
 void initializeNameAnonGlobalLegacyPassPass(PassRegistry&);
 void initializeNaryReassociateLegacyPassPass(PassRegistry&);
 void initializeNewGVNLegacyPassPass(PassRegistry&);
+void initializeNoAAResultsWrapperPassPass(PassRegistry&);
 void initializeObjCARCAAWrapperPassPass(PassRegistry&);
 void initializeObjCARCAPElimPass(PassRegistry&);
 void initializeObjCARCContractPass(PassRegistry&);
 void initializeObjCARCExpandPass(PassRegistry&);
 void initializeObjCARCOptPass(PassRegistry&);
 void initializeOptimizationRemarkEmitterWrapperPassPass(PassRegistry&);
 void initializeOptimizePHIsPass(PassRegistry&);
 void initializePAEvalPass(PassRegistry&);

lib/Analysis/AliasAnalysis.cpp

void AAResultsWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.addUsedIfAvailable<TypeBasedAAWrapperPass>();
   AU.addUsedIfAvailable<objcarc::ObjCARCAAWrapperPass>();
   AU.addUsedIfAvailable<GlobalsAAWrapperPass>();
   AU.addUsedIfAvailable<SCEVAAWrapperPass>();
   AU.addUsedIfAvailable<CFLAndersAAWrapperPass>();
   AU.addUsedIfAvailable<CFLSteensAAWrapperPass>();
 }
 
+NoAAResultsWrapperPass::NoAAResultsWrapperPass() : FunctionPass(ID) {
+  initializeNoAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
+}
+
+char NoAAResultsWrapperPass::ID = 0;
+
+INITIALIZE_PASS_BEGIN(NoAAResultsWrapperPass, "noaa",
+                      "No (conservative) Function Alias Analysis Results", false, true)
+INITIALIZE_PASS_END(NoAAResultsWrapperPass, "noaa",
+                    "No (conservative) Function Alias Analysis Results", false, true)
+
+FunctionPass *llvm::createNoAAResultsWrapperPass() {
+  return new NoAAResultsWrapperPass();
+}
+
+bool NoAAResultsWrapperPass::runOnFunction(Function &F) {
+  // NB! This *must* be reset before adding new AA results to the new
+  // AAResults object because in the legacy pass manager, each instance
+  // of these will refer to the *same* immutable analyses, registering and
+  // unregistering themselves with them. We need to carefully tear down the
+  // previous object first, in this case replacing it with an empty one, before
+  // registering new results.
+  AAR.reset(
+      new AAResults(getAnalysis<TargetLibraryInfoWrapperPass>().getTLI()));
+
+  // Analyses don't mutate the IR, so return false.
+  return false;
+}
+
+void NoAAResultsWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const {
+  AU.setPreservesAll();
+  AU.addRequired<TargetLibraryInfoWrapperPass>();
+}
+
 AAResults llvm::createLegacyPMAAResults(Pass &P, Function &F,
                                         BasicAAResult &BAR) {
   AAResults AAR(P.getAnalysis<TargetLibraryInfoWrapperPass>().getTLI());
 
   // Add in our explicitly constructed BasicAA results.
   if (!DisableBasicAA)
     AAR.addAAResult(BAR);
 

lib/Analysis/Analysis.cpp

void llvm::initializeAnalysis(PassRegistry &Registry) {
   initializeLazyValueInfoPrinterPass(Registry);
   initializeLintPass(Registry);
   initializeLoopInfoWrapperPassPass(Registry);
   initializeMemDepPrinterPass(Registry);
   initializeMemDerefPrinterPass(Registry);
   initializeMemoryDependenceWrapperPassPass(Registry);
   initializeModuleDebugInfoPrinterPass(Registry);
   initializeModuleSummaryIndexWrapperPassPass(Registry);
+  initializeNoAAResultsWrapperPassPass(Registry);
   initializeObjCARCAAWrapperPassPass(Registry);
   initializeOptimizationRemarkEmitterWrapperPassPass(Registry);
   initializePostDominatorTreeWrapperPassPass(Registry);
   initializeRegionInfoPassPass(Registry);
   initializeRegionViewerPass(Registry);
   initializeRegionPrinterPass(Registry);
   initializeRegionOnlyViewerPass(Registry);
   initializeRegionOnlyPrinterPass(Registry);

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
   SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
   GFI(),
   OptLevel(OL),
   DAGSize(0) {
     initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
     initializeBranchProbabilityInfoWrapperPassPass(
         *PassRegistry::getPassRegistry());
     initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
+    initializeNoAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
     initializeTargetLibraryInfoWrapperPassPass(
         *PassRegistry::getPassRegistry());
   }
 
 SelectionDAGISel::~SelectionDAGISel() {
   delete SDB;
   delete CurDAG;
   delete FuncInfo;
 }
 
 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
+  // Always require NoAAResultsWrapper, as we might end up using it for an
+  // optnone function.
+  AU.addRequired<NoAAResultsWrapperPass>();
+  if (OptLevel != CodeGenOpt::None)
     AU.addRequired<AAResultsWrapperPass>();
   AU.addRequired<GCModuleInfo>();
   AU.addRequired<StackProtector>();
   AU.addPreserved<StackProtector>();
   AU.addPreserved<GCModuleInfo>();
   AU.addRequired<TargetLibraryInfoWrapperPass>();
   if (UseMBPI && OptLevel != CodeGenOpt::None)
     AU.addRequired<BranchProbabilityInfoWrapperPass>();
   MachineFunctionPass::getAnalysisUsage(AU);
bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
   CodeGenOpt::Level NewOptLevel = OptLevel;
   if (OptLevel != CodeGenOpt::None && skipFunction(Fn))
     NewOptLevel = CodeGenOpt::None;
   OptLevelChanger OLC(*this, NewOptLevel);
 
   TII = MF->getSubtarget().getInstrInfo();
   TLI = MF->getSubtarget().getTargetLowering();
   RegInfo = &MF->getRegInfo();
-  AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
   LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
   GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
   ORE = make_unique<OptimizationRemarkEmitter>(&Fn);
 
+  if (OptLevel == CodeGenOpt::None)
+    AA = &getAnalysis<NoAAResultsWrapperPass>().getAAResults();
+  else
+    AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
+
   DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
 
   SplitCriticalSideEffectEdges(const_cast<Function &>(Fn));
 
   CurDAG->init(*MF, *ORE);
   FuncInfo->set(Fn, *MF, CurDAG);
 
   if (UseMBPI && OptLevel != CodeGenOpt::None)

lib/CodeGen/TargetPassConfig.cpp

 bool TargetPassConfig::usingDefaultRegAlloc() const {
   return RegAlloc.getNumOccurrences() == 0;
 }
 
 /// Add the minimum set of target-independent passes that are required for
 /// register allocation. No coalescing or scheduling.
 void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
   addPass(&PHIEliminationID, false);
-  addPass(&TwoAddressInstructionPassID, false);
+  addPass(createTwoAddressInstructionPass(getOptLevel()), false);
 
   if (RegAllocPass)
     addPass(RegAllocPass);
 }
 
 /// Add standard target-independent passes that are tightly coupled with
 /// optimized register allocation, including coalescing, machine instruction
 /// scheduling, and register allocation itself.
void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
   // Edge splitting is smarter with machine loop info.
   addPass(&MachineLoopInfoID, false);
   addPass(&PHIEliminationID, false);
 
   // Eventually, we want to run LiveIntervals before PHI elimination.
   if (EarlyLiveIntervals)
     addPass(&LiveIntervalsID, false);
 
-  addPass(&TwoAddressInstructionPassID, false);
+  addPass(createTwoAddressInstructionPass(getOptLevel()), false);
   addPass(&RegisterCoalescerID);
 
   // The machine scheduler may accidentally create disconnected components
   // when moving subregister definitions around, avoid this by splitting them to
   // separate vregs before. Splitting can also improve reg. allocation quality.
   addPass(&RenameIndependentSubregsID);
 
   // PreRA instruction scheduling.

lib/CodeGen/TwoAddressInstructionPass.cpp

class TwoAddressInstructionPass : public MachineFunctionPass {
   const TargetRegisterInfo *TRI;
   const InstrItineraryData *InstrItins;
   MachineRegisterInfo *MRI;
   LiveVariables *LV;
   LiveIntervals *LIS;
   AliasAnalysis *AA;
   CodeGenOpt::Level OptLevel;
 
+  // Whether we're permitted to use AliasAnalysis, via AAResultsWrapperPass.
+  bool UseAA;
+
   // The current basic block being processed.
   MachineBasicBlock *MBB;
 
   // Keep track the distance of a MI from the start of the current basic block.
   DenseMap<MachineInstr*, unsigned> DistanceMap;
 
   // Set of already processed instructions in the current block.
   SmallPtrSet<MachineInstr*, 8> Processed;
class TwoAddressInstructionPass : public MachineFunctionPass {
   typedef SmallVector<std::pair<unsigned, unsigned>, 4> TiedPairList;
   typedef SmallDenseMap<unsigned, TiedPairList> TiedOperandMap;
   bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
   void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
   void eliminateRegSequence(MachineBasicBlock::iterator&);
 
 public:
   static char ID; // Pass identification, replacement for typeid
-  TwoAddressInstructionPass() : MachineFunctionPass(ID) {
+  TwoAddressInstructionPass(bool UseAA = false)
+      : MachineFunctionPass(ID), UseAA(UseAA) {
     initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
+    if (UseAA)
       AU.addRequired<AAResultsWrapperPass>();
+    else
+      AU.addRequired<NoAAResultsWrapperPass>();
     AU.addUsedIfAvailable<LiveVariables>();
     AU.addPreserved<LiveVariables>();
     AU.addPreserved<SlotIndexes>();
     AU.addPreserved<LiveIntervals>();
     AU.addPreservedID(MachineLoopInfoID);
     AU.addPreservedID(MachineDominatorsID);
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
   /// Pass entry point.
   bool runOnMachineFunction(MachineFunction&) override;
 };
 } // end anonymous namespace
 
 char TwoAddressInstructionPass::ID = 0;
 INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, "twoaddressinstruction",
                 "Two-Address instruction pass", false, false)
+INITIALIZE_PASS_DEPENDENCY(NoAAResultsWrapperPass)
 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
 INITIALIZE_PASS_END(TwoAddressInstructionPass, "twoaddressinstruction",
                 "Two-Address instruction pass", false, false)
 
-char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
+//char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
+
+FunctionPass *llvm::createTwoAddressInstructionPass(bool UseAA) {
+  return new TwoAddressInstructionPass(UseAA);
+}
 
 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS);
 
 /// A two-address instruction has been converted to a three-address instruction
 /// to avoid clobbering a register. Try to sink it past the instruction that
 /// would kill the above mentioned register to reduce register pressure.
 bool TwoAddressInstructionPass::
 sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg,
bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
   MF = &Func;
   const TargetMachine &TM = MF->getTarget();
   MRI = &MF->getRegInfo();
   TII = MF->getSubtarget().getInstrInfo();
   TRI = MF->getSubtarget().getRegisterInfo();
   InstrItins = MF->getSubtarget().getInstrItineraryData();
   LV = getAnalysisIfAvailable<LiveVariables>();
   LIS = getAnalysisIfAvailable<LiveIntervals>();
+  if (UseAA)
     AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
+  else
+    AA = &getAnalysis<NoAAResultsWrapperPass>().getAAResults();
   OptLevel = TM.getOptLevel();
 
   bool MadeChange = false;
 
   DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
   DEBUG(dbgs() << "********** Function: "
         << MF->getName() << '\n');
 

lib/Target/NVPTX/NVPTXTargetMachine.cpp

 
 FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
   return nullptr; // No reg alloc
 }
 
 void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
   assert(!RegAllocPass && "NVPTX uses no regalloc!");
   addPass(&PHIEliminationID);
-  addPass(&TwoAddressInstructionPassID);
+  addPass(createTwoAddressInstructionPass(getOptLevel()));
 }
 
 void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
   assert(!RegAllocPass && "NVPTX uses no regalloc!");
 
   addPass(&ProcessImplicitDefsID);
   addPass(&LiveVariablesID);
   addPass(&MachineLoopInfoID);
   addPass(&PHIEliminationID);
 
-  addPass(&TwoAddressInstructionPassID);
+  addPass(createTwoAddressInstructionPass(getOptLevel()));
   addPass(&RegisterCoalescerID);
 
   // PreRA instruction scheduling.
   if (addPass(&MachineSchedulerID))
     printAndVerify("After Machine Scheduling");
 
 
   addPass(&StackSlotColoringID);

test/CodeGen/X86/O0-pipeline.ll

 ; CHECK-NEXT:       Remove unreachable blocks from the CFG
 ; CHECK-NEXT:       Inserts calls to mcount-like functions
 ; CHECK-NEXT:     Rewrite Symbols
 ; CHECK-NEXT:     FunctionPass Manager
 ; CHECK-NEXT:       Exception handling preparation
 ; CHECK-NEXT:       Safe Stack instrumentation pass
 ; CHECK-NEXT:       Insert stack protectors
 ; CHECK-NEXT:       Module Verifier
-; CHECK-NEXT:       Dominator Tree Construction
-; CHECK-NEXT:       Basic Alias Analysis (stateless AA impl)
-; CHECK-NEXT:       Function Alias Analysis Results
+; CHECK-NEXT:       No (conservative) Function Alias Analysis Results
 ; CHECK-NEXT:       X86 DAG->DAG Instruction Selection
 ; CHECK-NEXT:       X86 PIC Global Base Reg Initialization
 ; CHECK-NEXT:       Expand ISel Pseudo-instructions
 ; CHECK-NEXT:       Local Stack Slot Allocation
 ; CHECK-NEXT:       X86 WinAlloca Expander
 ; CHECK-NEXT:       Eliminate PHI nodes for register allocation
+; CHECK-NEXT:       No (conservative) Function Alias Analysis Results
 ; CHECK-NEXT:       Two-Address instruction pass
 ; CHECK-NEXT:       Fast Register Allocator
 ; CHECK-NEXT:       Bundle Machine CFG Edges
 ; CHECK-NEXT:       X86 FP Stackifier
 ; CHECK-NEXT:       Prologue/Epilogue Insertion & Frame Finalization
 ; CHECK-NEXT:       Post-RA pseudo instruction expansion pass
 ; CHECK-NEXT:       X86 pseudo instruction expansion pass
 ; CHECK-NEXT:       Analyze Machine Code For Garbage Collection

test/CodeGen/X86/pr32284.ll

 ; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    retl
 ;
 ; X86-O0-LABEL: foo:
 ; X86-O0:       # BB#0: # %entry
 ; X86-O0-NEXT:    subl $12, %esp
 ; X86-O0-NEXT:  .Lcfi0:
 ; X86-O0-NEXT:    .cfi_def_cfa_offset 16
-; X86-O0-NEXT:    movzbl c, %eax
-; X86-O0-NEXT:    testl %eax, %eax
-; X86-O0-NEXT:    setne %cl
-; X86-O0-NEXT:    movl %eax, %edx
-; X86-O0-NEXT:    movb %dl, %ch
-; X86-O0-NEXT:    testb %ch, %ch
+; X86-O0-NEXT:    movb c, %al
+; X86-O0-NEXT:    testb %al, %al
 ; X86-O0-NEXT:    setne {{[0-9]+}}(%esp)
-; X86-O0-NEXT:    movzbl %cl, %edx
-; X86-O0-NEXT:    subl %eax, %edx
-; X86-O0-NEXT:    setle %cl
-; X86-O0-NEXT:    # implicit-def: %EAX
-; X86-O0-NEXT:    movb %cl, %al
-; X86-O0-NEXT:    andl $1, %eax
-; X86-O0-NEXT:    kmovd %eax, %k0
-; X86-O0-NEXT:    kmovd %k0, %eax
+; X86-O0-NEXT:    movzbl c, %ecx
+; X86-O0-NEXT:    testl %ecx, %ecx
+; X86-O0-NEXT:    setne %al
+; X86-O0-NEXT:    movzbl %al, %edx
+; X86-O0-NEXT:    subl %ecx, %edx
+; X86-O0-NEXT:    setle %al
+; X86-O0-NEXT:    # implicit-def: %ECX
 ; X86-O0-NEXT:    movb %al, %cl
-; X86-O0-NEXT:    andb $1, %cl
-; X86-O0-NEXT:    movzbl %cl, %eax
-; X86-O0-NEXT:    movl %eax, {{[0-9]+}}(%esp)
+; X86-O0-NEXT:    andl $1, %ecx
+; X86-O0-NEXT:    kmovd %ecx, %k0
+; X86-O0-NEXT:    kmovd %k0, %ecx
+; X86-O0-NEXT:    movb %cl, %al
+; X86-O0-NEXT:    andb $1, %al
+; X86-O0-NEXT:    movzbl %al, %ecx
+; X86-O0-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
 ; X86-O0-NEXT:    movl %edx, (%esp) # 4-byte Spill
 ; X86-O0-NEXT:    addl $12, %esp
 ; X86-O0-NEXT:    retl
 ;
 ; X64-LABEL: foo:
 ; X64:       # BB#0: # %entry
 ; X64-NEXT:    movzbl {{.*}}(%rip), %eax
 ; X64-NEXT:    testb %al, %al
 ; X64-NEXT:    setne -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    xorl %ecx, %ecx
 ; X64-NEXT:    testl %eax, %eax
 ; X64-NEXT:    setne %cl
 ; X64-NEXT:    xorl %edx, %edx
 ; X64-NEXT:    cmpl %eax, %ecx
 ; X64-NEXT:    setle %dl
 ; X64-NEXT:    movl %edx, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    retq
 ;
 ; X64-O0-LABEL: foo:
 ; X64-O0:       # BB#0: # %entry
-; X64-O0-NEXT:    movzbl {{.*}}(%rip), %eax
-; X64-O0-NEXT:    movl %eax, %ecx
-; X64-O0-NEXT:    movb %cl, %dl
-; X64-O0-NEXT:    movl %ecx, %eax
-; X64-O0-NEXT:    testq %rcx, %rcx
-; X64-O0-NEXT:    setne %sil
-; X64-O0-NEXT:    testb %dl, %dl
+; X64-O0-NEXT:    movb {{.*}}(%rip), %al
+; X64-O0-NEXT:    testb %al, %al
 ; X64-O0-NEXT:    setne -{{[0-9]+}}(%rsp)
-; X64-O0-NEXT:    movzbl %sil, %edi
-; X64-O0-NEXT:    subl %eax, %edi
-; X64-O0-NEXT:    setle %dl
-; X64-O0-NEXT:    # implicit-def: %EAX
-; X64-O0-NEXT:    movb %dl, %al
-; X64-O0-NEXT:    andl $1, %eax
-; X64-O0-NEXT:    kmovd %eax, %k0
-; X64-O0-NEXT:    kmovd %k0, %eax
-; X64-O0-NEXT:    movb %al, %dl
-; X64-O0-NEXT:    andb $1, %dl
-; X64-O0-NEXT:    movzbl %dl, %eax
-; X64-O0-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
-; X64-O0-NEXT:    movl %edi, -{{[0-9]+}}(%rsp) # 4-byte Spill
+; X64-O0-NEXT:    movzbl {{.*}}(%rip), %ecx
+; X64-O0-NEXT:    testl %ecx, %ecx
+; X64-O0-NEXT:    setne %al
+; X64-O0-NEXT:    movzbl %al, %edx
+; X64-O0-NEXT:    subl %ecx, %edx
+; X64-O0-NEXT:    setle %al
+; X64-O0-NEXT:    # implicit-def: %ECX
+; X64-O0-NEXT:    movb %al, %cl
+; X64-O0-NEXT:    andl $1, %ecx
+; X64-O0-NEXT:    kmovd %ecx, %k0
+; X64-O0-NEXT:    kmovd %k0, %ecx
+; X64-O0-NEXT:    movb %cl, %al
+; X64-O0-NEXT:    andb $1, %al
+; X64-O0-NEXT:    movzbl %al, %ecx
+; X64-O0-NEXT:    movl %ecx, -{{[0-9]+}}(%rsp)
+; X64-O0-NEXT:    movl %edx, -{{[0-9]+}}(%rsp) # 4-byte Spill
 ; X64-O0-NEXT:    retq
 entry:
   %a = alloca i8, align 1
   %b = alloca i32, align 4
   %0 = load i8, i8* @c, align 1
   %conv = zext i8 %0 to i32
   %sub = sub nsw i32 0, %conv
   %conv1 = sext i32 %sub to i64