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Differential D31254

[SDAG] Fix zeroExtend assertion error
ClosedPublic

Authored by niravd on Mar 22 2017, 12:42 PM.

Details

Reviewers
RKSimon
bogner
Commits
rG0d229e0c79a9: Merging r298604:
rGe9ca32ae5261: [SDAG] Fix zeroExtend assertion error
rL300979: Merging r298604:
rL298604: [SDAG] Fix zeroExtend assertion error
Summary

Add missing CombineTo preventing deleted node from being returned in
visitZERO_EXTEND.

Fixes PR32284.

Diff Detail

Event Timeline

niravd created this revision.Mar 22 2017, 12:42 PM
RKSimon accepted this revision.Mar 23 2017, 6:36 AM

LGTM

This revision is now accepted and ready to land.Mar 23 2017, 6:36 AM
Closed by commit rL298604: [SDAG] Fix zeroExtend assertion error (authored by niravd). · Explain WhyMar 23 2017, 8:14 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
CodeGen/
SelectionDAG/
3 lines
test/
CodeGen/
X86/
32 lines

Diff 92687

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,271 Lines • ▼ Show 20 Lines if (ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
if (VT.isVector()) if (VT.isVector())
DoXform &= TLI.isVectorLoadExtDesirable(SDValue(N, 0)); DoXform &= TLI.isVectorLoadExtDesirable(SDValue(N, 0));
if (DoXform) { if (DoXform) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0); LoadSDNode *LN0 = cast<LoadSDNode>(N0);
SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT, SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
LN0->getChain(), LN0->getChain(),
LN0->getBasePtr(), N0.getValueType(), LN0->getBasePtr(), N0.getValueType(),
LN0->getMemOperand()); LN0->getMemOperand());
CombineTo(N, ExtLoad);
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
N0.getValueType(), ExtLoad); N0.getValueType(), ExtLoad);
CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N), ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
ISD::ZERO_EXTEND); ISD::ZERO_EXTEND);
CombineTo(N, ExtLoad);
return SDValue(N, 0); // Return N so it doesn't get rechecked! return SDValue(N, 0); // Return N so it doesn't get rechecked!
} }
} }
// fold (zext (load x)) to multiple smaller zextloads. // fold (zext (load x)) to multiple smaller zextloads.
// Only on illegal but splittable vectors. // Only on illegal but splittable vectors.
if (SDValue ExtLoad = CombineExtLoad(N)) if (SDValue ExtLoad = CombineExtLoad(N))
return ExtLoad; return ExtLoad;
▲ Show 20 Lines • Show All 9,026 Lines • Show Last 20 Lines

test/CodeGen/X86/pr32284.ll

  • This file was added.
; RUN: llc -O0 -mtriple=i686-unknown -mcpu=skx -o - %s
; RUN: llc -O0 -mtriple=x86_64-unknown -mcpu=skx -o - %s
; RUN: llc -mtriple=i686-unknown -mcpu=skx -o - %s
; RUN: llc -mtriple=x86_64-unknown -mcpu=skx -o - %s
@c = external constant i8, align 1
define void @foo() {
entry:
%a = alloca i8, align 1
%b = alloca i32, align 4
%0 = load i8, i8* @c, align 1
%conv = zext i8 %0 to i32
%sub = sub nsw i32 0, %conv
%conv1 = sext i32 %sub to i64
%sub2 = sub nsw i64 0, %conv1
%conv3 = trunc i64 %sub2 to i8
%tobool = icmp ne i8 %conv3, 0
%frombool = zext i1 %tobool to i8
store i8 %frombool, i8* %a, align 1
%1 = load i8, i8* @c, align 1
%tobool4 = icmp ne i8 %1, 0
%lnot = xor i1 %tobool4, true
%lnot5 = xor i1 %lnot, true
%conv6 = zext i1 %lnot5 to i32
%2 = load i8, i8* @c, align 1
%conv7 = zext i8 %2 to i32
%cmp = icmp sle i32 %conv6, %conv7
%conv8 = zext i1 %cmp to i32
store i32 %conv8, i32* %b, align 4
ret void
}