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AMDGPU: Fix folding reg_sequence into copy to phys reg
ClosedPublic

Authored by arsenm on Mar 21 2017, 10:00 AM.

Reviewers

arsenm

Summary

This was producing an illegal reg_sequence defining
a physical register with virtual register inputs.

ping

r299997

This revision is now accepted and ready to land.Apr 11 2017, 3:43 PM

Path

Size

lib/

Target/

AMDGPU/

4 lines

test/

CodeGen/

AMDGPU/

13 lines

Show First 20 Lines • Show All 192 Lines • ▼ Show 20 Lines	static bool foldVGPRCopyIntoRegSequence(MachineInstr &MI,

if (!MRI.hasOneUse(DstReg))		if (!MRI.hasOneUse(DstReg))
return false;		return false;

MachineInstr &CopyUse = *MRI.use_instr_begin(DstReg);		MachineInstr &CopyUse = *MRI.use_instr_begin(DstReg);
if (!CopyUse.isCopy())		if (!CopyUse.isCopy())
return false;		return false;

		// It is illegal to have vreg inputs to a physreg defining reg_sequence.
		if (TargetRegisterInfo::isPhysicalRegister(CopyUse.getOperand(0).getReg()))
		return false;

const TargetRegisterClass SrcRC, DstRC;		const TargetRegisterClass SrcRC, DstRC;
std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI);		std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI);

if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI))		if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI))
return false;		return false;

// TODO: Could have multiple extracts?		// TODO: Could have multiple extracts?
unsigned SubReg = CopyUse.getOperand(1).getSubReg();		unsigned SubReg = CopyUse.getOperand(1).getSubReg();
▲ Show 20 Lines • Show All 255 Lines • Show Last 20 Lines

	Show First 20 Lines • Show All 177 Lines • ▼ Show 20 Lines
	; separate comment			; separate comment
	v_bfrev_b32_e32 v0, 1			v_bfrev_b32_e32 v0, 1

	; trailing comment			; trailing comment
	; extra comment			; extra comment
	", ""()			", ""()
	ret void			ret void
	}			}

				; FIXME: Should not have intermediate sgprs
				; CHECK-LABEL: {{^}}i64_imm_input_phys_vgpr:
				; CHECK: s_mov_b32 s1, 0
				; CHECK: s_mov_b32 s0, 0x1e240
				; CHECK: v_mov_b32_e32 v0, s0
				; CHECK: v_mov_b32_e32 v1, s1
				; CHECK: use v[0:1]
				define void @i64_imm_input_phys_vgpr() {
				entry:
				call void asm sideeffect "; use $0 ", "{VGPR0_VGPR1}"(i64 123456)
				ret void
				}