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[Mips] Fix for decoding DINS instruction - disassembler
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Authored by spetrovic on Mar 17 2017, 5:01 AM.

Details

Summary

This patch fixes decoding of size and position for DINSM and DINSU instructions. It's different for DINS and DINSM/DINSU, I also changed test case because in this format: dinsm $4, $5, 10, 1, if position and size are 10 and 1 it's DINS, not DINSM variant. After this fix I'm able to add test case for LLVM assembler ( https://reviews.llvm.org/D30988 ).

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Repository
rL LLVM

Event Timeline

spetrovic created this revision.Mar 17 2017, 5:01 AM
sdardis accepted this revision.Mar 20 2017, 7:39 AM

LGTM.

This revision is now accepted and ready to land.Mar 20 2017, 7:39 AM
This revision was automatically updated to reflect the committed changes.