[X86][AVX512] Add missing entries to EVEX2VEX tables

[aymanmus]

Summary

evex2vex pass defines 2 tables which maps EVEX instructions to their VEX identical when possible. Adding all missing entries.

[craig.topper]

lib/Target/X86/X86InstrTablesInfo.h

50

Why was this one removed? A review that says "add missing entries" and then removes some without explanation is confusing.

202

The VEX instructions with a C in it are treated as commutable. The EVEX versions without a C shouldn't become commutable when they are compressed.

[aymanmus]

lib/Target/X86/X86InstrTablesInfo.h

50

The VEX encoded instructions of these entries are defined for intrinsics.
The patch is here to stabilize the tables before pushing the tablegen backend which will replace them.

202

In this stage of the compiler there is no difference between MAX and MAXC, They have the same exact encoding and this difference is not relevant from this point and on.

[craig.topper]

LGTM

lib/Target/X86/X86InstrTablesInfo.h

static const X86EvexToVexCompressTableEntry X86EvexToVex128CompressTable[] = {
   { X86::VADDSSZrm              ,  X86::VADDSSrm                 },
   { X86::VADDSSZrm_Int          ,  X86::VADDSSrm_Int             },
   { X86::VADDSSZrr              ,  X86::VADDSSrr                 },
   { X86::VADDSSZrr_Int          ,  X86::VADDSSrr_Int             },
   { X86::VCOMISDZrm             ,  X86::VCOMISDrm                },
   { X86::VCOMISDZrr             ,  X86::VCOMISDrr                },
   { X86::VCOMISSZrm             ,  X86::VCOMISSrm                },
   { X86::VCOMISSZrr             ,  X86::VCOMISSrr                },
-  { X86::VCVTSD2SI64Zrm         ,  X86::VCVTSD2SI64rm            },
   { X86::VCVTSD2SI64Zrr         ,  X86::VCVTSD2SI64rr            },
-  { X86::VCVTSD2SIZrm           ,  X86::VCVTSD2SIrm              },
   { X86::VCVTSD2SIZrr           ,  X86::VCVTSD2SIrr              },
   { X86::VCVTSD2SSZrm           ,  X86::VCVTSD2SSrm              },
   { X86::VCVTSD2SSZrr           ,  X86::VCVTSD2SSrr              },
   { X86::VCVTSI2SDZrm           ,  X86::VCVTSI2SDrm              },
   { X86::VCVTSI2SDZrm_Int       ,  X86::Int_VCVTSI2SDrm          },
   { X86::VCVTSI2SDZrr           ,  X86::VCVTSI2SDrr              },
   { X86::VCVTSI2SDZrr_Int       ,  X86::Int_VCVTSI2SDrr          },
   { X86::VCVTSI2SSZrm           ,  X86::VCVTSI2SSrm              },
   { X86::VCVTSI2SSZrm_Int       ,  X86::Int_VCVTSI2SSrm          },
   { X86::VCVTSI2SSZrr           ,  X86::VCVTSI2SSrr              },
   { X86::VCVTSI2SSZrr_Int       ,  X86::Int_VCVTSI2SSrr          },
+  { X86::VCVTSI642SDZrm         ,  X86::VCVTSI2SD64rm            },
+  { X86::VCVTSI642SDZrm_Int     ,  X86::Int_VCVTSI2SD64rm        },
+  { X86::VCVTSI642SDZrr         ,  X86::VCVTSI2SD64rr            },
+  { X86::VCVTSI642SDZrr_Int     ,  X86::Int_VCVTSI2SD64rr        },
+  { X86::VCVTSI642SSZrm         ,  X86::VCVTSI2SS64rm            },
+  { X86::VCVTSI642SSZrm_Int     ,  X86::Int_VCVTSI2SS64rm        },
+  { X86::VCVTSI642SSZrr         ,  X86::VCVTSI2SS64rr            },
+  { X86::VCVTSI642SSZrr_Int     ,  X86::Int_VCVTSI2SS64rr        },
   { X86::VCVTSS2SDZrm           ,  X86::VCVTSS2SDrm              },
   { X86::VCVTSS2SDZrr           ,  X86::VCVTSS2SDrr              },
-  { X86::VCVTSS2SI64Zrm         ,  X86::VCVTSS2SI64rm            },
   { X86::VCVTSS2SI64Zrr         ,  X86::VCVTSS2SI64rr            },
-  { X86::VCVTSS2SIZrm           ,  X86::VCVTSS2SIrm              },
   { X86::VCVTSS2SIZrr           ,  X86::VCVTSS2SIrr              },
   { X86::VCVTTSD2SI64Zrm        ,  X86::VCVTTSD2SI64rm           },
   { X86::VCVTTSD2SI64Zrm_Int    ,  X86::Int_VCVTTSD2SI64rm       },
   { X86::VCVTTSD2SI64Zrr        ,  X86::VCVTTSD2SI64rr           },
   { X86::VCVTTSD2SI64Zrr_Int    ,  X86::Int_VCVTTSD2SI64rr       },
   { X86::VCVTTSD2SIZrm          ,  X86::VCVTTSD2SIrm             },
   { X86::VCVTTSD2SIZrm_Int      ,  X86::Int_VCVTTSD2SIrm         },
   { X86::VCVTTSD2SIZrr          ,  X86::VCVTTSD2SIrr             },
static const X86EvexToVexCompressTableEntry X86EvexToVex128CompressTable[] = {
   { X86::VDIVSDZrm              ,  X86::VDIVSDrm                 },
   { X86::VDIVSDZrm_Int          ,  X86::VDIVSDrm_Int             },
   { X86::VDIVSDZrr              ,  X86::VDIVSDrr                 },
   { X86::VDIVSDZrr_Int          ,  X86::VDIVSDrr_Int             },
   { X86::VDIVSSZrm              ,  X86::VDIVSSrm                 },
   { X86::VDIVSSZrm_Int          ,  X86::VDIVSSrm_Int             },
   { X86::VDIVSSZrr              ,  X86::VDIVSSrr                 },
   { X86::VDIVSSZrr_Int          ,  X86::VDIVSSrr_Int             },
+  { X86::VEXTRACTPSZmr          ,  X86::VEXTRACTPSmr             },
+  { X86::VEXTRACTPSZrr          ,  X86::VEXTRACTPSrr             },
   { X86::VFMADD132SDZm          ,  X86::VFMADD132SDm             },
   { X86::VFMADD132SDZm_Int      ,  X86::VFMADD132SDm_Int         },
   { X86::VFMADD132SDZr          ,  X86::VFMADD132SDr             },
   { X86::VFMADD132SDZr_Int      ,  X86::VFMADD132SDr_Int         },
   { X86::VFMADD132SSZm          ,  X86::VFMADD132SSm             },
   { X86::VFMADD132SSZm_Int      ,  X86::VFMADD132SSm_Int         },
   { X86::VFMADD132SSZr          ,  X86::VFMADD132SSr             },
   { X86::VFMADD132SSZr_Int      ,  X86::VFMADD132SSr_Int         },
static const X86EvexToVexCompressTableEntry X86EvexToVex128CompressTable[] = {
   { X86::VFNMSUB231SDZm         ,  X86::VFNMSUB231SDm            },
   { X86::VFNMSUB231SDZm_Int     ,  X86::VFNMSUB231SDm_Int        },
   { X86::VFNMSUB231SDZr         ,  X86::VFNMSUB231SDr            },
   { X86::VFNMSUB231SDZr_Int     ,  X86::VFNMSUB231SDr_Int        },
   { X86::VFNMSUB231SSZm         ,  X86::VFNMSUB231SSm            },
   { X86::VFNMSUB231SSZm_Int     ,  X86::VFNMSUB231SSm_Int        },
   { X86::VFNMSUB231SSZr         ,  X86::VFNMSUB231SSr            },
   { X86::VFNMSUB231SSZr_Int     ,  X86::VFNMSUB231SSr_Int        },
+  { X86::VINSERTPSZrm           ,  X86::VINSERTPSrm              },
+  { X86::VINSERTPSZrr           ,  X86::VINSERTPSrr              },
   { X86::VMAXCSDZrm             ,  X86::VMAXCSDrm                },
   { X86::VMAXCSDZrr             ,  X86::VMAXCSDrr                },
   { X86::VMAXCSSZrm             ,  X86::VMAXCSSrm                },
   { X86::VMAXCSSZrr             ,  X86::VMAXCSSrr                },
-  { X86::VMAXSDZrm              ,  X86::VMAXSDrm                 },
+  { X86::VMAXSDZrm              ,  X86::VMAXCSDrm                },
   { X86::VMAXSDZrm_Int          ,  X86::VMAXSDrm_Int             },
-  { X86::VMAXSDZrr              ,  X86::VMAXSDrr                 },
+  { X86::VMAXSDZrr              ,  X86::VMAXCSDrr                },
   { X86::VMAXSDZrr_Int          ,  X86::VMAXSDrr_Int             },
-  { X86::VMAXSSZrm              ,  X86::VMAXSSrm                 },
+  { X86::VMAXSSZrm              ,  X86::VMAXCSSrm                },
   { X86::VMAXSSZrm_Int          ,  X86::VMAXSSrm_Int             },
-  { X86::VMAXSSZrr              ,  X86::VMAXSSrr                 },
+  { X86::VMAXSSZrr              ,  X86::VMAXCSSrr                },
   { X86::VMAXSSZrr_Int          ,  X86::VMAXSSrr_Int             },
   { X86::VMINCSDZrm             ,  X86::VMINCSDrm                },
   { X86::VMINCSDZrr             ,  X86::VMINCSDrr                },
   { X86::VMINCSSZrm             ,  X86::VMINCSSrm                },
   { X86::VMINCSSZrr             ,  X86::VMINCSSrr                },
-  { X86::VMINSDZrm              ,  X86::VMINSDrm                 },
+  { X86::VMINSDZrm              ,  X86::VMINCSDrm                },
   { X86::VMINSDZrm_Int          ,  X86::VMINSDrm_Int             },
-  { X86::VMINSDZrr              ,  X86::VMINSDrr                 },
+  { X86::VMINSDZrr              ,  X86::VMINCSDrr                },
   { X86::VMINSDZrr_Int          ,  X86::VMINSDrr_Int             },
-  { X86::VMINSSZrm              ,  X86::VMINSSrm                 },
+  { X86::VMINSSZrm              ,  X86::VMINCSSrm                },
   { X86::VMINSSZrm_Int          ,  X86::VMINSSrm_Int             },
-  { X86::VMINSSZrr              ,  X86::VMINSSrr                 },
+  { X86::VMINSSZrr              ,  X86::VMINCSSrr                },
   { X86::VMINSSZrr_Int          ,  X86::VMINSSrr_Int             },
   { X86::VMOV64toSDZrr          ,  X86::VMOV64toSDrr             },
   { X86::VMOVDI2SSZrm           ,  X86::VMOVDI2SSrm              },
   { X86::VMOVDI2SSZrr           ,  X86::VMOVDI2SSrr              },
+  { X86::VMOVSDto64Zmr          ,  X86::VMOVSDto64mr             },
+  { X86::VMOVSDto64Zrr          ,  X86::VMOVSDto64rr             },
   { X86::VMOVSDZmr              ,  X86::VMOVSDmr                 },
   { X86::VMOVSDZrm              ,  X86::VMOVSDrm                 },
   { X86::VMOVSDZrr              ,  X86::VMOVSDrr                 },
+  { X86::VMOVSDZrr_REV          ,  X86::VMOVSDrr_REV             },
+  { X86::VMOVSS2DIZmr           ,  X86::VMOVSS2DImr              },
+  { X86::VMOVSS2DIZrr           ,  X86::VMOVSS2DIrr              },
   { X86::VMOVSSZmr              ,  X86::VMOVSSmr                 },
   { X86::VMOVSSZrm              ,  X86::VMOVSSrm                 },
   { X86::VMOVSSZrr              ,  X86::VMOVSSrr                 },
   { X86::VMOVSSZrr_REV          ,  X86::VMOVSSrr_REV             },
   { X86::VMULSDZrm              ,  X86::VMULSDrm                 },
   { X86::VMULSDZrm_Int          ,  X86::VMULSDrm_Int             },
   { X86::VMULSDZrr              ,  X86::VMULSDrr                 },
   { X86::VMULSDZrr_Int          ,  X86::VMULSDrr_Int             },
static const X86EvexToVexCompressTableEntry X86EvexToVex128CompressTable[] = {
   { X86::VSUBSSZrm_Int          ,  X86::VSUBSSrm_Int             },
   { X86::VSUBSSZrr              ,  X86::VSUBSSrr                 },
   { X86::VSUBSSZrr_Int          ,  X86::VSUBSSrr_Int             },
   { X86::VUCOMISDZrm            ,  X86::VUCOMISDrm               },
   { X86::VUCOMISDZrr            ,  X86::VUCOMISDrr               },
   { X86::VUCOMISSZrm            ,  X86::VUCOMISSrm               },
   { X86::VUCOMISSZrr            ,  X86::VUCOMISSrr               },
 
+  { X86::VMOV64toPQIZrm         ,   X86::VMOV64toPQIrm           },
   { X86::VMOV64toPQIZrr         ,   X86::VMOV64toPQIrr           },
   { X86::VMOV64toSDZrr          ,   X86::VMOV64toSDrr            },
   { X86::VMOVDI2PDIZrm          ,   X86::VMOVDI2PDIrm            },
   { X86::VMOVDI2PDIZrr          ,   X86::VMOVDI2PDIrr            },
   { X86::VMOVLHPSZrr            ,   X86::VMOVLHPSrr              },
   { X86::VMOVHLPSZrr            ,   X86::VMOVHLPSrr              },
   { X86::VMOVPDI2DIZmr          ,   X86::VMOVPDI2DImr            },
   { X86::VMOVPDI2DIZrr          ,   X86::VMOVPDI2DIrr            },
   { X86::VMOVPQI2QIZmr          ,   X86::VMOVPQI2QImr            },
+  { X86::VMOVPQI2QIZrr          ,   X86::VMOVPQI2QIrr            },
+  { X86::VMOVPQIto64Zmr         ,   X86::VMOVPQIto64mr           },
   { X86::VMOVPQIto64Zrr         ,   X86::VMOVPQIto64rr           },
   { X86::VMOVQI2PQIZrm          ,   X86::VMOVQI2PQIrm            },
   { X86::VMOVZPQILo2PQIZrr      ,   X86::VMOVZPQILo2PQIrr        },
 
   { X86::VPEXTRBZmr             ,   X86::VPEXTRBmr               },
   { X86::VPEXTRBZrr             ,   X86::VPEXTRBrr               },
   { X86::VPEXTRDZmr             ,   X86::VPEXTRDmr               },
   { X86::VPEXTRDZrr             ,   X86::VPEXTRDrr               },
   { X86::VPEXTRQZmr             ,   X86::VPEXTRQmr               },
   { X86::VPEXTRQZrr             ,   X86::VPEXTRQrr               },
   { X86::VPEXTRWZmr             ,   X86::VPEXTRWmr               },
   { X86::VPEXTRWZrr             ,   X86::VPEXTRWri               },
+  { X86::VPEXTRWZrr_REV         ,   X86::VPEXTRWrr_REV           },
 
   { X86::VPINSRBZrm             ,   X86::VPINSRBrm               },
   { X86::VPINSRBZrr             ,   X86::VPINSRBrr               },
   { X86::VPINSRDZrm             ,   X86::VPINSRDrm               },
   { X86::VPINSRDZrr             ,   X86::VPINSRDrr               },
   { X86::VPINSRQZrm             ,   X86::VPINSRQrm               },
   { X86::VPINSRQZrr             ,   X86::VPINSRQrr               },
   { X86::VPINSRWZrm             ,   X86::VPINSRWrmi              },
   { X86::VPINSRWZrr             ,   X86::VPINSRWrri              },
 
   // EVEX 128 with corresponding VEX.
   { X86::VADDPDZ128rm           ,    X86::VADDPDrm               },
   { X86::VADDPDZ128rr           ,    X86::VADDPDrr               },
   { X86::VADDPSZ128rm           ,    X86::VADDPSrm               },
   { X86::VADDPSZ128rr           ,    X86::VADDPSrr               },
   { X86::VANDNPDZ128rm          ,    X86::VANDNPDrm              },
   { X86::VANDNPDZ128rr          ,    X86::VANDNPDrr              },
   { X86::VANDNPSZ128rm          ,    X86::VANDNPSrm              },
   { X86::VANDNPSZ128rr          ,    X86::VANDNPSrr              },
   { X86::VANDPDZ128rm           ,    X86::VANDPDrm               },
   { X86::VANDPDZ128rr           ,    X86::VANDPDrr               },
   { X86::VANDPSZ128rm           ,    X86::VANDPSrm               },
   { X86::VANDPSZ128rr           ,    X86::VANDPSrr               },
+  { X86::VBROADCASTI32X2Z128m   ,    X86::VPBROADCASTQrm         },
+  { X86::VBROADCASTI32X2Z128r   ,    X86::VPBROADCASTQrr         },
   { X86::VBROADCASTSSZ128m      ,    X86::VBROADCASTSSrm         },
   { X86::VBROADCASTSSZ128r      ,    X86::VBROADCASTSSrr         },
   { X86::VCVTDQ2PDZ128rm        ,    X86::VCVTDQ2PDrm            },
   { X86::VCVTDQ2PDZ128rr        ,    X86::VCVTDQ2PDrr            },
   { X86::VCVTDQ2PSZ128rm        ,    X86::VCVTDQ2PSrm            },
   { X86::VCVTDQ2PSZ128rr        ,    X86::VCVTDQ2PSrr            },
   { X86::VCVTPD2DQZ128rm        ,    X86::VCVTPD2DQrm            },
   { X86::VCVTPD2DQZ128rr        ,    X86::VCVTPD2DQrr            },
static const X86EvexToVexCompressTableEntry X86EvexToVex128CompressTable[] = {
   { X86::VFNMSUB231PDZ128m      ,    X86::VFNMSUB231PDm          },
   { X86::VFNMSUB231PDZ128r      ,    X86::VFNMSUB231PDr          },
   { X86::VFNMSUB231PSZ128m      ,    X86::VFNMSUB231PSm          },
   { X86::VFNMSUB231PSZ128r      ,    X86::VFNMSUB231PSr          },
   { X86::VMAXCPDZ128rm          ,    X86::VMAXCPDrm              },
   { X86::VMAXCPDZ128rr          ,    X86::VMAXCPDrr              },
   { X86::VMAXCPSZ128rm          ,    X86::VMAXCPSrm              },
   { X86::VMAXCPSZ128rr          ,    X86::VMAXCPSrr              },
-  { X86::VMAXPDZ128rm           ,    X86::VMAXPDrm               },
-  { X86::VMAXPDZ128rr           ,    X86::VMAXPDrr               },
-  { X86::VMAXPSZ128rm           ,    X86::VMAXPSrm               },
-  { X86::VMAXPSZ128rr           ,    X86::VMAXPSrr               },
+  { X86::VMAXPDZ128rm           ,    X86::VMAXCPDrm              },
+  { X86::VMAXPDZ128rr           ,    X86::VMAXCPDrr              },
+  { X86::VMAXPSZ128rm           ,    X86::VMAXCPSrm              },
+  { X86::VMAXPSZ128rr           ,    X86::VMAXCPSrr              },
   { X86::VMINCPDZ128rm          ,    X86::VMINCPDrm              },
   { X86::VMINCPDZ128rr          ,    X86::VMINCPDrr              },
   { X86::VMINCPSZ128rm          ,    X86::VMINCPSrm              },
   { X86::VMINCPSZ128rr          ,    X86::VMINCPSrr              },
-  { X86::VMINPDZ128rm           ,    X86::VMINPDrm               },
-  { X86::VMINPDZ128rr           ,    X86::VMINPDrr               },
-  { X86::VMINPSZ128rm           ,    X86::VMINPSrm               },
-  { X86::VMINPSZ128rr           ,    X86::VMINPSrr               },
+  { X86::VMINPDZ128rm           ,    X86::VMINCPDrm              },
+  { X86::VMINPDZ128rr           ,    X86::VMINCPDrr              },
+  { X86::VMINPSZ128rm           ,    X86::VMINCPSrm              },
+  { X86::VMINPSZ128rr           ,    X86::VMINCPSrr              },
   { X86::VMOVAPDZ128mr          ,    X86::VMOVAPDmr              },
   { X86::VMOVAPDZ128rm          ,    X86::VMOVAPDrm              },
   { X86::VMOVAPDZ128rr          ,    X86::VMOVAPDrr              },
   { X86::VMOVAPDZ128rr_REV      ,    X86::VMOVAPDrr_REV          },
   { X86::VMOVAPSZ128mr          ,    X86::VMOVAPSmr              },
   { X86::VMOVAPSZ128rm          ,    X86::VMOVAPSrm              },
   { X86::VMOVAPSZ128rr          ,    X86::VMOVAPSrr              },
   { X86::VMOVAPSZ128rr_REV      ,    X86::VMOVAPSrr_REV          },
static const X86EvexToVexCompressTableEntry X86EvexToVex128CompressTable[] = {
   { X86::VPADDWZ128rm           ,    X86::VPADDWrm               },
   { X86::VPADDWZ128rr           ,    X86::VPADDWrr               },
   { X86::VPALIGNRZ128rmi        ,    X86::VPALIGNRrmi            },
   { X86::VPALIGNRZ128rri        ,    X86::VPALIGNRrri            },
   { X86::VPANDDZ128rm           ,    X86::VPANDrm                },
   { X86::VPANDDZ128rr           ,    X86::VPANDrr                },
   { X86::VPANDQZ128rm           ,    X86::VPANDrm                },
   { X86::VPANDQZ128rr           ,    X86::VPANDrr                },
+  { X86::VPANDNDZ128rm          ,    X86::VPANDNrm               },
+  { X86::VPANDNDZ128rr          ,    X86::VPANDNrr               },
+  { X86::VPANDNQZ128rm          ,    X86::VPANDNrm               },
+  { X86::VPANDNQZ128rr          ,    X86::VPANDNrr               },
   { X86::VPAVGBZ128rm           ,    X86::VPAVGBrm               },
   { X86::VPAVGBZ128rr           ,    X86::VPAVGBrr               },
   { X86::VPAVGWZ128rm           ,    X86::VPAVGWrm               },
   { X86::VPAVGWZ128rr           ,    X86::VPAVGWrr               },
   { X86::VPBROADCASTBZ128m      ,    X86::VPBROADCASTBrm         },
   { X86::VPBROADCASTBZ128r      ,    X86::VPBROADCASTBrr         },
   { X86::VPBROADCASTDZ128m      ,    X86::VPBROADCASTDrm         },
   { X86::VPBROADCASTDZ128r      ,    X86::VPBROADCASTDrr         },
static const X86EvexToVexCompressTableEntry X86EvexToVex256CompressTable[] = {
   { X86::VANDNPDZ256rm          ,     X86::VANDNPDYrm            },
   { X86::VANDNPDZ256rr          ,     X86::VANDNPDYrr            },
   { X86::VANDNPSZ256rm          ,     X86::VANDNPSYrm            },
   { X86::VANDNPSZ256rr          ,     X86::VANDNPSYrr            },
   { X86::VANDPDZ256rm           ,     X86::VANDPDYrm             },
   { X86::VANDPDZ256rr           ,     X86::VANDPDYrr             },
   { X86::VANDPSZ256rm           ,     X86::VANDPSYrm             },
   { X86::VANDPSZ256rr           ,     X86::VANDPSYrr             },
+  { X86::VBROADCASTF32X2Z256m   ,     X86::VBROADCASTSDYrm       },
+  { X86::VBROADCASTF32X2Z256r   ,     X86::VBROADCASTSDYrr       },
+  { X86::VBROADCASTF32X4Z256rm  ,     X86::VBROADCASTF128        },
+  { X86::VBROADCASTI32X2Z256m   ,     X86::VPBROADCASTQYrm       },
+  { X86::VBROADCASTI32X2Z256r   ,     X86::VPBROADCASTQYrr       },
+  { X86::VBROADCASTI32X4Z256rm  ,     X86::VBROADCASTI128        },
   { X86::VBROADCASTSDZ256m      ,     X86::VBROADCASTSDYrm       },
   { X86::VBROADCASTSDZ256r      ,     X86::VBROADCASTSDYrr       },
   { X86::VBROADCASTSSZ256m      ,     X86::VBROADCASTSSYrm       },
   { X86::VBROADCASTSSZ256r      ,     X86::VBROADCASTSSYrr       },
   { X86::VCVTDQ2PDZ256rm        ,     X86::VCVTDQ2PDYrm          },
   { X86::VCVTDQ2PDZ256rr        ,     X86::VCVTDQ2PDYrr          },
   { X86::VCVTDQ2PSZ256rm        ,     X86::VCVTDQ2PSYrm          },
   { X86::VCVTDQ2PSZ256rr        ,     X86::VCVTDQ2PSYrr          },
static const X86EvexToVexCompressTableEntry X86EvexToVex256CompressTable[] = {
   { X86::VINSERTI32x4Z256rm     ,    X86::VINSERTI128rm          },
   { X86::VINSERTI64x2Z256rm     ,    X86::VINSERTI128rm          },
   { X86::VINSERTI32x4Z256rr     ,    X86::VINSERTI128rr          },
   { X86::VINSERTI64x2Z256rr     ,    X86::VINSERTI128rr          },
   { X86::VMAXCPDZ256rm          ,     X86::VMAXCPDYrm            },
   { X86::VMAXCPDZ256rr          ,     X86::VMAXCPDYrr            },
   { X86::VMAXCPSZ256rm          ,     X86::VMAXCPSYrm            },
   { X86::VMAXCPSZ256rr          ,     X86::VMAXCPSYrr            },
-  { X86::VMAXPDZ256rm           ,     X86::VMAXPDYrm             },
-  { X86::VMAXPDZ256rr           ,     X86::VMAXPDYrr             },
-  { X86::VMAXPSZ256rm           ,     X86::VMAXPSYrm             },
-  { X86::VMAXPSZ256rr           ,     X86::VMAXPSYrr             },
+  { X86::VMAXPDZ256rm           ,     X86::VMAXCPDYrm            },
+  { X86::VMAXPDZ256rr           ,     X86::VMAXCPDYrr            },
+  { X86::VMAXPSZ256rm           ,     X86::VMAXCPSYrm            },
+  { X86::VMAXPSZ256rr           ,     X86::VMAXCPSYrr            },
   { X86::VMINCPDZ256rm          ,     X86::VMINCPDYrm            },
   { X86::VMINCPDZ256rr          ,     X86::VMINCPDYrr            },
   { X86::VMINCPSZ256rm          ,     X86::VMINCPSYrm            },
   { X86::VMINCPSZ256rr          ,     X86::VMINCPSYrr            },
-  { X86::VMINPDZ256rm           ,     X86::VMINPDYrm             },
-  { X86::VMINPDZ256rr           ,     X86::VMINPDYrr             },
-  { X86::VMINPSZ256rm           ,     X86::VMINPSYrm             },
-  { X86::VMINPSZ256rr           ,     X86::VMINPSYrr             },
+  { X86::VMINPDZ256rm           ,     X86::VMINCPDYrm            },
+  { X86::VMINPDZ256rr           ,     X86::VMINCPDYrr            },
+  { X86::VMINPSZ256rm           ,     X86::VMINCPSYrm            },
+  { X86::VMINPSZ256rr           ,     X86::VMINCPSYrr            },
   { X86::VMOVAPDZ256mr          ,     X86::VMOVAPDYmr            },
   { X86::VMOVAPDZ256rm          ,     X86::VMOVAPDYrm            },
   { X86::VMOVAPDZ256rr          ,     X86::VMOVAPDYrr            },
   { X86::VMOVAPDZ256rr_REV      ,     X86::VMOVAPDYrr_REV        },
   { X86::VMOVAPSZ256mr          ,     X86::VMOVAPSYmr            },
   { X86::VMOVAPSZ256rm          ,     X86::VMOVAPSYrm            },
   { X86::VMOVAPSZ256rr          ,     X86::VMOVAPSYrr            },
   { X86::VMOVAPSZ256rr_REV      ,     X86::VMOVAPSYrr_REV        },
static const X86EvexToVexCompressTableEntry X86EvexToVex256CompressTable[] = {
   { X86::VPADDWZ256rm           ,     X86::VPADDWYrm             },
   { X86::VPADDWZ256rr           ,     X86::VPADDWYrr             },
   { X86::VPALIGNRZ256rmi        ,     X86::VPALIGNRYrmi          },
   { X86::VPALIGNRZ256rri        ,     X86::VPALIGNRYrri          },
   { X86::VPANDDZ256rm           ,     X86::VPANDYrm              },
   { X86::VPANDDZ256rr           ,     X86::VPANDYrr              },
   { X86::VPANDQZ256rm           ,     X86::VPANDYrm              },
   { X86::VPANDQZ256rr           ,     X86::VPANDYrr              },
+  { X86::VPANDNDZ256rm          ,     X86::VPANDNYrm             },
+  { X86::VPANDNDZ256rr          ,     X86::VPANDNYrr             },
+  { X86::VPANDNQZ256rm          ,     X86::VPANDNYrm             },
+  { X86::VPANDNQZ256rr          ,     X86::VPANDNYrr             },
   { X86::VPAVGBZ256rm           ,     X86::VPAVGBYrm             },
   { X86::VPAVGBZ256rr           ,     X86::VPAVGBYrr             },
   { X86::VPAVGWZ256rm           ,     X86::VPAVGWYrm             },
   { X86::VPAVGWZ256rr           ,     X86::VPAVGWYrr             },
   { X86::VPBROADCASTBZ256m      ,     X86::VPBROADCASTBYrm       },
   { X86::VPBROADCASTBZ256r      ,     X86::VPBROADCASTBYrr       },
   { X86::VPBROADCASTDZ256m      ,     X86::VPBROADCASTDYrm       },
   { X86::VPBROADCASTDZ256r      ,     X86::VPBROADCASTDYrr       },

test/CodeGen/X86/avx512-mov.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding| FileCheck %s
 
 define i32 @test1(float %x) {
 ; CHECK-LABEL: test1:
 ; CHECK:       ## BB#0:
-; CHECK-NEXT:    vmovd %xmm0, %eax ## encoding: [0x62,0xf1,0x7d,0x08,0x7e,0xc0]
+; CHECK-NEXT:    vmovd %xmm0, %eax ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x7e,0xc0]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
    %res = bitcast float %x to i32
    ret i32 %res
 }
 
 define <4 x i32> @test2(i32 %x) {
 ; CHECK-LABEL: test2:
 ; CHECK:       ## BB#0:

test/CodeGen/X86/avx512-vbroadcasti128.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512vl | FileCheck %s --check-prefix=X64-AVX512 --check-prefix=X64-AVX512VL
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512bw,+avx512vl | FileCheck %s --check-prefix=X64-AVX512 --check-prefix=X64-AVX512BWVL
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefix=X64-AVX512 --check-prefix=X64-AVX512DQVL
 
 ;
 ; 128-bit Subvector Broadcast to 256-bit
 ;
 
 define <4 x double> @test_broadcast_2f64_4f64(<2 x double> *%p) nounwind {
 ; X64-AVX512VL-LABEL: test_broadcast_2f64_4f64:
 ; X64-AVX512VL:       ## BB#0:
-; X64-AVX512VL-NEXT:    vbroadcastf32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X64-AVX512VL-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX512VL-NEXT:    vaddpd {{.*}}(%rip), %ymm0, %ymm0
 ; X64-AVX512VL-NEXT:    retq
 ;
 ; X64-AVX512BWVL-LABEL: test_broadcast_2f64_4f64:
 ; X64-AVX512BWVL:       ## BB#0:
-; X64-AVX512BWVL-NEXT:    vbroadcastf32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X64-AVX512BWVL-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX512BWVL-NEXT:    vaddpd {{.*}}(%rip), %ymm0, %ymm0
 ; X64-AVX512BWVL-NEXT:    retq
 ;
 ; X64-AVX512DQVL-LABEL: test_broadcast_2f64_4f64:
 ; X64-AVX512DQVL:       ## BB#0:
 ; X64-AVX512DQVL-NEXT:    vbroadcastf64x2 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX512DQVL-NEXT:    vaddpd {{.*}}(%rip), %ymm0, %ymm0
 ; X64-AVX512DQVL-NEXT:    retq
  %1 = load <2 x double>, <2 x double> *%p
  %2 = shufflevector <2 x double> %1, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
  %3 = fadd <4 x double> %2, <double 1.0, double 2.0, double 3.0, double 4.0>
  ret <4 x double> %3
 }
 
 define <4 x i64> @test_broadcast_2i64_4i64(<2 x i64> *%p) nounwind {
 ; X64-AVX512VL-LABEL: test_broadcast_2i64_4i64:
 ; X64-AVX512VL:       ## BB#0:
-; X64-AVX512VL-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X64-AVX512VL-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX512VL-NEXT:    vpaddq {{.*}}(%rip), %ymm0, %ymm0
 ; X64-AVX512VL-NEXT:    retq
 ;
 ; X64-AVX512BWVL-LABEL: test_broadcast_2i64_4i64:
 ; X64-AVX512BWVL:       ## BB#0:
-; X64-AVX512BWVL-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X64-AVX512BWVL-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX512BWVL-NEXT:    vpaddq {{.*}}(%rip), %ymm0, %ymm0
 ; X64-AVX512BWVL-NEXT:    retq
 ;
 ; X64-AVX512DQVL-LABEL: test_broadcast_2i64_4i64:
 ; X64-AVX512DQVL:       ## BB#0:
 ; X64-AVX512DQVL-NEXT:    vbroadcasti64x2 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX512DQVL-NEXT:    vpaddq {{.*}}(%rip), %ymm0, %ymm0
 ; X64-AVX512DQVL-NEXT:    retq
  %1 = load <2 x i64>, <2 x i64> *%p
  %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
  %3 = add <4 x i64> %2, <i64 1, i64 2, i64 3, i64 4>
  ret <4 x i64> %3
 }
 
 define <8 x float> @test_broadcast_4f32_8f32(<4 x float> *%p) nounwind {
 ; X64-AVX512-LABEL: test_broadcast_4f32_8f32:
 ; X64-AVX512:       ## BB#0:
-; X64-AVX512-NEXT:    vbroadcastf32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X64-AVX512-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX512-NEXT:    vaddps {{.*}}(%rip), %ymm0, %ymm0
 ; X64-AVX512-NEXT:    retq
  %1 = load <4 x float>, <4 x float> *%p
  %2 = shufflevector <4 x float> %1, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
  %3 = fadd <8 x float> %2, <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>
  ret <8 x float> %3
 }
 
 define <8 x i32> @test_broadcast_4i32_8i32(<4 x i32> *%p) nounwind {
 ; X64-AVX512-LABEL: test_broadcast_4i32_8i32:
 ; X64-AVX512:       ## BB#0:
-; X64-AVX512-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X64-AVX512-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX512-NEXT:    vpaddd {{.*}}(%rip), %ymm0, %ymm0
 ; X64-AVX512-NEXT:    retq
  %1 = load <4 x i32>, <4 x i32> *%p
  %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
  %3 = add <8 x i32> %2, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
  ret <8 x i32> %3
 }
 
 define <16 x i16> @test_broadcast_8i16_16i16(<8 x i16> *%p) nounwind {
 ; X64-AVX512-LABEL: test_broadcast_8i16_16i16:
 ; X64-AVX512:       ## BB#0:
-; X64-AVX512-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X64-AVX512-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX512-NEXT:    vpaddw {{.*}}(%rip), %ymm0, %ymm0
 ; X64-AVX512-NEXT:    retq
  %1 = load <8 x i16>, <8 x i16> *%p
  %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  %3  = add <16 x i16> %2, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 16>
  ret <16 x i16> %3
 }
 
 define <32 x i8> @test_broadcast_16i8_32i8(<16 x i8> *%p) nounwind {
 ; X64-AVX512-LABEL: test_broadcast_16i8_32i8:
 ; X64-AVX512:       ## BB#0:
-; X64-AVX512-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X64-AVX512-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX512-NEXT:    vpaddb {{.*}}(%rip), %ymm0, %ymm0
 ; X64-AVX512-NEXT:    retq
  %1 = load <16 x i8>, <16 x i8> *%p
  %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  %3 = add <32 x i8> %2, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32>
  ret <32 x i8> %3
 }
 

  %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
  %3 = add <16 x i32> %2, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16>
  ret <16 x i32> %3
 }
 
 define <32 x i16> @test_broadcast_8i16_32i16(<8 x i16> *%p) nounwind {
 ; X64-AVX512VL-LABEL: test_broadcast_8i16_32i16:
 ; X64-AVX512VL:       ## BB#0:
-; X64-AVX512VL-NEXT:    vbroadcasti32x4 {{.*#+}} ymm1 = mem[0,1,2,3,0,1,2,3]
+; X64-AVX512VL-NEXT:    vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
 ; X64-AVX512VL-NEXT:    vpaddw {{.*}}(%rip), %ymm1, %ymm0
 ; X64-AVX512VL-NEXT:    vpaddw {{.*}}(%rip), %ymm1, %ymm1
 ; X64-AVX512VL-NEXT:    retq
 ;
 ; X64-AVX512BWVL-LABEL: test_broadcast_8i16_32i16:
 ; X64-AVX512BWVL:       ## BB#0:
 ; X64-AVX512BWVL-NEXT:    vbroadcasti32x4 {{.*#+}} zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
 ; X64-AVX512BWVL-NEXT:    vpaddw {{.*}}(%rip), %zmm0, %zmm0
 ; X64-AVX512BWVL-NEXT:    retq
 ;
 ; X64-AVX512DQVL-LABEL: test_broadcast_8i16_32i16:
 ; X64-AVX512DQVL:       ## BB#0:
-; X64-AVX512DQVL-NEXT:    vbroadcasti32x4 {{.*#+}} ymm1 = mem[0,1,2,3,0,1,2,3]
+; X64-AVX512DQVL-NEXT:    vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
 ; X64-AVX512DQVL-NEXT:    vpaddw {{.*}}(%rip), %ymm1, %ymm0
 ; X64-AVX512DQVL-NEXT:    vpaddw {{.*}}(%rip), %ymm1, %ymm1
 ; X64-AVX512DQVL-NEXT:    retq
  %1 = load <8 x i16>, <8 x i16> *%p
  %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  %3  = add <32 x i16> %2, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22, i16 23, i16 24, i16 25, i16 26, i16 27, i16 28, i16 29, i16 30, i16 31, i16 32>
  ret <32 x i16> %3
 }
 
 define <64 x i8> @test_broadcast_16i8_64i8(<16 x i8> *%p) nounwind {
 ; X64-AVX512VL-LABEL: test_broadcast_16i8_64i8:
 ; X64-AVX512VL:       ## BB#0:
-; X64-AVX512VL-NEXT:    vbroadcasti32x4 {{.*#+}} ymm1 = mem[0,1,2,3,0,1,2,3]
+; X64-AVX512VL-NEXT:    vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
 ; X64-AVX512VL-NEXT:    vpaddb {{.*}}(%rip), %ymm1, %ymm0
 ; X64-AVX512VL-NEXT:    vpaddb {{.*}}(%rip), %ymm1, %ymm1
 ; X64-AVX512VL-NEXT:    retq
 ;
 ; X64-AVX512BWVL-LABEL: test_broadcast_16i8_64i8:
 ; X64-AVX512BWVL:       ## BB#0:
 ; X64-AVX512BWVL-NEXT:    vbroadcasti32x4 {{.*#+}} zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
 ; X64-AVX512BWVL-NEXT:    vpaddb {{.*}}(%rip), %zmm0, %zmm0
 ; X64-AVX512BWVL-NEXT:    retq
 ;
 ; X64-AVX512DQVL-LABEL: test_broadcast_16i8_64i8:
 ; X64-AVX512DQVL:       ## BB#0:
-; X64-AVX512DQVL-NEXT:    vbroadcasti32x4 {{.*#+}} ymm1 = mem[0,1,2,3,0,1,2,3]
+; X64-AVX512DQVL-NEXT:    vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
 ; X64-AVX512DQVL-NEXT:    vpaddb {{.*}}(%rip), %ymm1, %ymm0
 ; X64-AVX512DQVL-NEXT:    vpaddb {{.*}}(%rip), %ymm1, %ymm1
 ; X64-AVX512DQVL-NEXT:    retq
  %1 = load <16 x i8>, <16 x i8> *%p
  %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  %3 = add <64 x i8> %2, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39, i8 40, i8 41, i8 42, i8 43, i8 44, i8 45, i8 46, i8 47, i8 48, i8 49, i8 50, i8 51, i8 52, i8 53, i8 54, i8 55, i8 56, i8 57, i8 58, i8 59, i8 60, i8 61, i8 62, i8 63, i8 64>
  ret <64 x i8> %3
 }

test/CodeGen/X86/avx512dqvl-intrinsics.ll

 define <8 x float>@test_int_x86_avx512_mask_broadcastf32x2_256(<4 x float> %x0, <8 x float> %x2, i8 %x3) {
 ; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf32x2_256:
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    kmovb %edi, %k1 ## encoding: [0xc5,0xf9,0x92,0xcf]
 ; CHECK-NEXT:    vbroadcastf32x2 %xmm0, %ymm1 {%k1} ## encoding: [0x62,0xf2,0x7d,0x29,0x19,0xc8]
 ; CHECK-NEXT:    ## ymm1 {%k1} = xmm0[0,1,0,1,0,1,0,1]
 ; CHECK-NEXT:    vbroadcastf32x2 %xmm0, %ymm2 {%k1} {z} ## encoding: [0x62,0xf2,0x7d,0xa9,0x19,0xd0]
 ; CHECK-NEXT:    ## ymm2 {%k1} {z} = xmm0[0,1,0,1,0,1,0,1]
-; CHECK-NEXT:    vbroadcastf32x2 %xmm0, %ymm0 ## encoding: [0x62,0xf2,0x7d,0x28,0x19,0xc0]
-; CHECK-NEXT:    ## ymm0 = xmm0[0,1,0,1,0,1,0,1]
+; CHECK-NEXT:    vbroadcastsd %xmm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x19,0xc0]
 ; CHECK-NEXT:    vaddps %ymm2, %ymm1, %ymm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf4,0x58,0xca]
 ; CHECK-NEXT:    vaddps %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf4,0x58,0xc0]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %res = call <8 x float> @llvm.x86.avx512.mask.broadcastf32x2.256(<4 x float>  %x0, <8 x float> %x2, i8 %x3)
   %res1 = call <8 x float> @llvm.x86.avx512.mask.broadcastf32x2.256(<4 x float> %x0, <8 x float> zeroinitializer, i8 %x3)
   %res2 = call <8 x float> @llvm.x86.avx512.mask.broadcastf32x2.256(<4 x float> %x0, <8 x float> %x2, i8 -1)
   %res3 = fadd <8 x float> %res, %res1
   %res4 = fadd <8 x float> %res3, %res2
   ret <8 x float> %res4
 }
 
 declare <8 x i32> @llvm.x86.avx512.mask.broadcasti32x2.256(<4 x i32>, <8 x i32>, i8)
 
 define <8 x i32>@test_int_x86_avx512_mask_broadcasti32x2_256(<4 x i32> %x0, <8 x i32> %x2, i8 %x3, i64 * %y_ptr) {
 ; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x2_256:
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    kmovb %edi, %k1 ## encoding: [0xc5,0xf9,0x92,0xcf]
 ; CHECK-NEXT:    vbroadcasti32x2 (%rsi), %ymm1 {%k1} ## encoding: [0x62,0xf2,0x7d,0x29,0x59,0x0e]
 ; CHECK-NEXT:    ## ymm1 {%k1} = mem[0,1,0,1,0,1,0,1]
 ; CHECK-NEXT:    vbroadcasti32x2 %xmm0, %ymm2 {%k1} {z} ## encoding: [0x62,0xf2,0x7d,0xa9,0x59,0xd0]
 ; CHECK-NEXT:    ## ymm2 {%k1} {z} = xmm0[0,1,0,1,0,1,0,1]
-; CHECK-NEXT:    vbroadcasti32x2 %xmm0, %ymm0 ## encoding: [0x62,0xf2,0x7d,0x28,0x59,0xc0]
-; CHECK-NEXT:    ## ymm0 = xmm0[0,1,0,1,0,1,0,1]
+; CHECK-NEXT:    vpbroadcastq %xmm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x59,0xc0]
 ; CHECK-NEXT:    vpaddd %ymm0, %ymm2, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xed,0xfe,0xc0]
 ; CHECK-NEXT:    vpaddd %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf5,0xfe,0xc0]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %y_64  = load i64, i64 * %y_ptr
   %y_v2i64 = insertelement <2 x i64> undef, i64 %y_64, i32 0
   %y = bitcast <2 x i64> %y_v2i64 to <4 x i32>
   %res = call <8 x i32> @llvm.x86.avx512.mask.broadcasti32x2.256(<4 x i32>  %y, <8 x i32> %x2, i8 %x3)
   %res1 = call <8 x i32> @llvm.x86.avx512.mask.broadcasti32x2.256(<4 x i32> %x0, <8 x i32> zeroinitializer, i8 %x3)
   %res2 = call <8 x i32> @llvm.x86.avx512.mask.broadcasti32x2.256(<4 x i32> %x0, <8 x i32> %x2, i8 -1)
   %res3 = add <8 x i32> %res, %res1
   %res4 = add <8 x i32> %res3, %res2
   ret <8 x i32> %res4
 }
 
 declare <4 x i32> @llvm.x86.avx512.mask.broadcasti32x2.128(<4 x i32>, <4 x i32>, i8)
 
 define <4 x i32>@test_int_x86_avx512_mask_broadcasti32x2_128(<4 x i32> %x0, <4 x i32> %x2, i8 %x3) {
 ; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x2_128:
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    kmovb %edi, %k1 ## encoding: [0xc5,0xf9,0x92,0xcf]
 ; CHECK-NEXT:    vbroadcasti32x2 %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf2,0x7d,0x09,0x59,0xc8]
 ; CHECK-NEXT:    vbroadcasti32x2 %xmm0, %xmm2 {%k1} {z} ## encoding: [0x62,0xf2,0x7d,0x89,0x59,0xd0]
-; CHECK-NEXT:    vbroadcasti32x2 %xmm0, %xmm0 ## encoding: [0x62,0xf2,0x7d,0x08,0x59,0xc0]
+; CHECK-NEXT:    vpbroadcastq %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x59,0xc0]
 ; CHECK-NEXT:    vpaddd %xmm2, %xmm1, %xmm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf1,0xfe,0xca]
 ; CHECK-NEXT:    vpaddd %xmm0, %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf1,0xfe,0xc0]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %res = call <4 x i32> @llvm.x86.avx512.mask.broadcasti32x2.128(<4 x i32>  %x0, <4 x i32> %x2, i8 %x3)
   %res1 = call <4 x i32> @llvm.x86.avx512.mask.broadcasti32x2.128(<4 x i32> %x0, <4 x i32> zeroinitializer, i8 %x3)
   %res2 = call <4 x i32> @llvm.x86.avx512.mask.broadcasti32x2.128(<4 x i32> %x0, <4 x i32> %x2, i8 -1)
   %res3 = add <4 x i32> %res, %res1
   %res4 = add <4 x i32> %res3, %res2

test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll

; CHECK-NEXT:    retq ## encoding: [0xc3]
   ret <8 x i32> %res
 }
 
 declare <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)
 
 define <4 x i32> @test_mask_andnot_epi32_rr_128(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_mask_andnot_epi32_rr_128:
 ; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpandnd %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x08,0xdf,0xc1]
+; CHECK-NEXT:    vpandn %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xdf,0xc1]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
   ret <4 x i32> %res
 }
 
 define <4 x i32> @test_mask_andnot_epi32_rrk_128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask) {
 ; CHECK-LABEL: test_mask_andnot_epi32_rrk_128:
 ; CHECK:       ## BB#0:

 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
   ret <4 x i32> %res
 }
 
 define <4 x i32> @test_mask_andnot_epi32_rm_128(<4 x i32> %a, <4 x i32>* %ptr_b) {
 ; CHECK-LABEL: test_mask_andnot_epi32_rm_128:
 ; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpandnd (%rdi), %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x08,0xdf,0x07]
+; CHECK-NEXT:    vpandn (%rdi), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xdf,0x07]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %b = load <4 x i32>, <4 x i32>* %ptr_b
   %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
   ret <4 x i32> %res
 }
 
 define <4 x i32> @test_mask_andnot_epi32_rmk_128(<4 x i32> %a, <4 x i32>* %ptr_b, <4 x i32> %passThru, i8 %mask) {
 ; CHECK-LABEL: test_mask_andnot_epi32_rmk_128:
; CHECK-NEXT:    retq ## encoding: [0xc3]
   ret <4 x i32> %res
 }
 
 declare <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)
 
 define <8 x i32> @test_mask_andnot_epi32_rr_256(<8 x i32> %a, <8 x i32> %b) {
 ; CHECK-LABEL: test_mask_andnot_epi32_rr_256:
 ; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpandnd %ymm1, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x28,0xdf,0xc1]
+; CHECK-NEXT:    vpandn %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xdf,0xc1]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
   ret <8 x i32> %res
 }
 
 define <8 x i32> @test_mask_andnot_epi32_rrk_256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask) {
 ; CHECK-LABEL: test_mask_andnot_epi32_rrk_256:
 ; CHECK:       ## BB#0:

 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
   ret <8 x i32> %res
 }
 
 define <8 x i32> @test_mask_andnot_epi32_rm_256(<8 x i32> %a, <8 x i32>* %ptr_b) {
 ; CHECK-LABEL: test_mask_andnot_epi32_rm_256:
 ; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpandnd (%rdi), %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x28,0xdf,0x07]
+; CHECK-NEXT:    vpandn (%rdi), %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xdf,0x07]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %b = load <8 x i32>, <8 x i32>* %ptr_b
   %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
   ret <8 x i32> %res
 }
 
 define <8 x i32> @test_mask_andnot_epi32_rmk_256(<8 x i32> %a, <8 x i32>* %ptr_b, <8 x i32> %passThru, i8 %mask) {
 ; CHECK-LABEL: test_mask_andnot_epi32_rmk_256:
; CHECK-NEXT:    retq ## encoding: [0xc3]
   ret <8 x i32> %res
 }
 
 declare <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)
 
 define <2 x i64> @test_mask_andnot_epi64_rr_128(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_mask_andnot_epi64_rr_128:
 ; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpandnq %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0xfd,0x08,0xdf,0xc1]
+; CHECK-NEXT:    vpandn %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xdf,0xc1]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 -1)
   ret <2 x i64> %res
 }
 
 define <2 x i64> @test_mask_andnot_epi64_rrk_128(<2 x i64> %a, <2 x i64> %b, <2 x i64> %passThru, i8 %mask) {
 ; CHECK-LABEL: test_mask_andnot_epi64_rrk_128:
 ; CHECK:       ## BB#0:

 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 %mask)
   ret <2 x i64> %res
 }
 
 define <2 x i64> @test_mask_andnot_epi64_rm_128(<2 x i64> %a, <2 x i64>* %ptr_b) {
 ; CHECK-LABEL: test_mask_andnot_epi64_rm_128:
 ; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpandnq (%rdi), %xmm0, %xmm0 ## encoding: [0x62,0xf1,0xfd,0x08,0xdf,0x07]
+; CHECK-NEXT:    vpandn (%rdi), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xdf,0x07]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %b = load <2 x i64>, <2 x i64>* %ptr_b
   %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 -1)
   ret <2 x i64> %res
 }
 
 define <2 x i64> @test_mask_andnot_epi64_rmk_128(<2 x i64> %a, <2 x i64>* %ptr_b, <2 x i64> %passThru, i8 %mask) {
 ; CHECK-LABEL: test_mask_andnot_epi64_rmk_128:
; CHECK-NEXT:    retq ## encoding: [0xc3]
   ret <2 x i64> %res
 }
 
 declare <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)
 
 define <4 x i64> @test_mask_andnot_epi64_rr_256(<4 x i64> %a, <4 x i64> %b) {
 ; CHECK-LABEL: test_mask_andnot_epi64_rr_256:
 ; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpandnq %ymm1, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0xfd,0x28,0xdf,0xc1]
+; CHECK-NEXT:    vpandn %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xdf,0xc1]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 -1)
   ret <4 x i64> %res
 }
 
 define <4 x i64> @test_mask_andnot_epi64_rrk_256(<4 x i64> %a, <4 x i64> %b, <4 x i64> %passThru, i8 %mask) {
 ; CHECK-LABEL: test_mask_andnot_epi64_rrk_256:
 ; CHECK:       ## BB#0:

 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 %mask)
   ret <4 x i64> %res
 }
 
 define <4 x i64> @test_mask_andnot_epi64_rm_256(<4 x i64> %a, <4 x i64>* %ptr_b) {
 ; CHECK-LABEL: test_mask_andnot_epi64_rm_256:
 ; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpandnq (%rdi), %ymm0, %ymm0 ## encoding: [0x62,0xf1,0xfd,0x28,0xdf,0x07]
+; CHECK-NEXT:    vpandn (%rdi), %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xdf,0x07]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %b = load <4 x i64>, <4 x i64>* %ptr_b
   %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 -1)
   ret <4 x i64> %res
 }
 
 define <4 x i64> @test_mask_andnot_epi64_rmk_256(<4 x i64> %a, <4 x i64>* %ptr_b, <4 x i64> %passThru, i8 %mask) {
 ; CHECK-LABEL: test_mask_andnot_epi64_rmk_256:

test/CodeGen/X86/avx512vl-logic.ll

entry:
   %x = and <8 x i32> %a2, %b
   ret <8 x i32> %x
 }
 
 define <8 x i32> @vpandnd256(<8 x i32> %a, <8 x i32> %b) nounwind uwtable readnone ssp {
 ; CHECK-LABEL: vpandnd256:
 ; CHECK:       ## BB#0: ## %entry
 ; CHECK-NEXT:    vpaddd {{.*}}(%rip){1to8}, %ymm0, %ymm1
-; CHECK-NEXT:    vpandnd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    vpandn %ymm1, %ymm0, %ymm0
 ; CHECK-NEXT:    retq
 entry:
   ; Force the execution domain with an add.
   %a2 = add <8 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
   %b2 = xor <8 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
   %x = and <8 x i32> %a2, %b2
   ret <8 x i32> %x
 }
entry:
   %x = and <4 x i64> %a2, %b
   ret <4 x i64> %x
 }
 
 define <4 x i64> @vpandnq256(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
 ; CHECK-LABEL: vpandnq256:
 ; CHECK:       ## BB#0: ## %entry
 ; CHECK-NEXT:    vpaddq {{.*}}(%rip){1to4}, %ymm0, %ymm0
-; CHECK-NEXT:    vpandnq %ymm0, %ymm1, %ymm0
+; CHECK-NEXT:    vpandn %ymm0, %ymm1, %ymm0
 ; CHECK-NEXT:    retq
 entry:
   ; Force the execution domain with an add.
   %a2 = add <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
   %b2 = xor <4 x i64> %b, <i64 -1, i64 -1, i64 -1, i64 -1>
   %x = and <4 x i64> %a2, %b2
   ret <4 x i64> %x
 }
entry:
   %x = and <4 x i32> %a2, %b
   ret <4 x i32> %x
 }
 
 define <4 x i32> @vpandnd128(<4 x i32> %a, <4 x i32> %b) nounwind uwtable readnone ssp {
 ; CHECK-LABEL: vpandnd128:
 ; CHECK:       ## BB#0: ## %entry
 ; CHECK-NEXT:    vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
-; CHECK-NEXT:    vpandnd %xmm0, %xmm1, %xmm0
+; CHECK-NEXT:    vpandn %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    retq
 entry:
   ; Force the execution domain with an add.
   %a2 = add <4 x i32> %a, <i32 1, i32 1, i32 1, i32 1>
   %b2 = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
   %x = and <4 x i32> %a2, %b2
   ret <4 x i32> %x
 }
entry:
   %x = and <2 x i64> %a2, %b
   ret <2 x i64> %x
 }
 
 define <2 x i64> @vpandnq128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
 ; CHECK-LABEL: vpandnq128:
 ; CHECK:       ## BB#0: ## %entry
 ; CHECK-NEXT:    vpaddq {{.*}}(%rip), %xmm0, %xmm0
-; CHECK-NEXT:    vpandnq %xmm0, %xmm1, %xmm0
+; CHECK-NEXT:    vpandn %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    retq
 entry:
   ; Force the execution domain with an add.
   %a2 = add <2 x i64> %a, <i64 1, i64 1>
   %b2 = xor <2 x i64> %b, <i64 -1, i64 -1>
   %x = and <2 x i64> %a2, %b2
   ret <2 x i64> %x
 }

test/CodeGen/X86/evex-to-vex-compress.mir

body: |
   ; CHECK: %ymm0 = VPANDYrm                    %ymm0, %rip, 1, _, %rax, _
   %ymm0 = VPANDDZ256rm                         %ymm0, %rip, 1, _, %rax, _                     
   ; CHECK: %ymm0 = VPANDYrr                    %ymm0, %ymm1  
   %ymm0 = VPANDDZ256rr                         %ymm0, %ymm1                                   
   ; CHECK: %ymm0 = VPANDYrm                    %ymm0, %rip, 1, _, %rax, _
   %ymm0 = VPANDQZ256rm                         %ymm0, %rip, 1, _, %rax, _                     
   ; CHECK: %ymm0 = VPANDYrr                    %ymm0, %ymm1
   %ymm0 = VPANDQZ256rr                         %ymm0, %ymm1                                   
+  ; CHECK: %ymm0 = VPANDNYrm                    %ymm0, %rip, 1, _, %rax, _
+  %ymm0 = VPANDNDZ256rm                         %ymm0, %rip, 1, _, %rax, _                     
+  ; CHECK: %ymm0 = VPANDNYrr                    %ymm0, %ymm1  
+  %ymm0 = VPANDNDZ256rr                         %ymm0, %ymm1                                   
+  ; CHECK: %ymm0 = VPANDNYrm                    %ymm0, %rip, 1, _, %rax, _
+  %ymm0 = VPANDNQZ256rm                         %ymm0, %rip, 1, _, %rax, _                     
+  ; CHECK: %ymm0 = VPANDNYrr                    %ymm0, %ymm1
+  %ymm0 = VPANDNQZ256rr                         %ymm0, %ymm1                                   
   ; CHECK: %ymm0 = VPAVGBYrm                   %ymm0, %rip, 1, _, %rax, _
   %ymm0 = VPAVGBZ256rm                         %ymm0, %rip, 1, _, %rax, _                     
   ; CHECK: %ymm0 = VPAVGBYrr                   %ymm0, %ymm1
   %ymm0 = VPAVGBZ256rr                         %ymm0, %ymm1                                   
   ; CHECK: %ymm0 = VPAVGWYrm                   %ymm0, %rip, 1, _, %rax, _
   %ymm0 = VPAVGWZ256rm                         %ymm0, %rip, 1, _, %rax, _                     
   ; CHECK: %ymm0 = VPAVGWYrr                   %ymm0, %ymm1
   %ymm0 = VPAVGWZ256rr                         %ymm0, %ymm1                                   
body: |
   ; CHECK: %ymm0 = VMAXCPDYrm                  %ymm0, %rip, 1, _, %rax, _
   %ymm0 = VMAXCPDZ256rm                        %ymm0, %rip, 1, _, %rax, _                     
   ; CHECK: %ymm0 = VMAXCPDYrr                  %ymm0, %ymm1
   %ymm0 = VMAXCPDZ256rr                        %ymm0, %ymm1                                   
   ; CHECK: %ymm0 = VMAXCPSYrm                  %ymm0, %rip, 1, _, %rax, _
   %ymm0 = VMAXCPSZ256rm                        %ymm0, %rip, 1, _, %rax, _                     
   ; CHECK: %ymm0 = VMAXCPSYrr                  %ymm0, %ymm1
   %ymm0 = VMAXCPSZ256rr                        %ymm0, %ymm1                                   
-  ; CHECK: %ymm0 = VMAXPDYrm                   %ymm0, %rip, 1, _, %rax, _
+  ; CHECK: %ymm0 = VMAXCPDYrm                  %ymm0, %rip, 1, _, %rax, _
   %ymm0 = VMAXPDZ256rm                         %ymm0, %rip, 1, _, %rax, _                     
-  ; CHECK: %ymm0 = VMAXPDYrr                   %ymm0, %ymm1
+  ; CHECK: %ymm0 = VMAXCPDYrr                  %ymm0, %ymm1
   %ymm0 = VMAXPDZ256rr                         %ymm0, %ymm1                                   
-  ; CHECK: %ymm0 = VMAXPSYrm                   %ymm0, %rip, 1, _, %rax, _
+  ; CHECK: %ymm0 = VMAXCPSYrm                  %ymm0, %rip, 1, _, %rax, _
   %ymm0 = VMAXPSZ256rm                         %ymm0, %rip, 1, _, %rax, _                     
-  ; CHECK: %ymm0 = VMAXPSYrr                   %ymm0, %ymm1
+  ; CHECK: %ymm0 = VMAXCPSYrr                  %ymm0, %ymm1
   %ymm0 = VMAXPSZ256rr                         %ymm0, %ymm1                                   
   ; CHECK: %ymm0 = VMINCPDYrm                  %ymm0, %rip, 1, _, %rax, _
   %ymm0 = VMINCPDZ256rm                        %ymm0, %rip, 1, _, %rax, _                     
   ; CHECK: %ymm0 = VMINCPDYrr                  %ymm0, %ymm1
   %ymm0 = VMINCPDZ256rr                        %ymm0, %ymm1                                   
   ; CHECK: %ymm0 = VMINCPSYrm                  %ymm0, %rip, 1, _, %rax, _
   %ymm0 = VMINCPSZ256rm                        %ymm0, %rip, 1, _, %rax, _                     
   ; CHECK: %ymm0 = VMINCPSYrr                  %ymm0, %ymm1
   %ymm0 = VMINCPSZ256rr                        %ymm0, %ymm1                                   
-  ; CHECK: %ymm0 = VMINPDYrm                   %ymm0, %rip, 1, _, %rax, _
+  ; CHECK: %ymm0 = VMINCPDYrm                  %ymm0, %rip, 1, _, %rax, _
   %ymm0 = VMINPDZ256rm                         %ymm0, %rip, 1, _, %rax, _                     
-  ; CHECK: %ymm0 = VMINPDYrr                   %ymm0, %ymm1
+  ; CHECK: %ymm0 = VMINCPDYrr                  %ymm0, %ymm1
   %ymm0 = VMINPDZ256rr                         %ymm0, %ymm1                                   
-  ; CHECK: %ymm0 = VMINPSYrm                   %ymm0, %rip, 1, _, %rax, _
+  ; CHECK: %ymm0 = VMINCPSYrm                  %ymm0, %rip, 1, _, %rax, _
   %ymm0 = VMINPSZ256rm                         %ymm0, %rip, 1, _, %rax, _                     
-  ; CHECK: %ymm0 = VMINPSYrr                   %ymm0, %ymm1
+  ; CHECK: %ymm0 = VMINCPSYrr                  %ymm0, %ymm1
   %ymm0 = VMINPSZ256rr                         %ymm0, %ymm1                                   
   ; CHECK: %ymm0 = VXORPDYrm                   %ymm0, %rip, 1, _, %rax, _
   %ymm0 = VXORPDZ256rm                         %ymm0, %rip, 1, _, %rax, _                     
   ; CHECK: %ymm0 = VXORPDYrr                   %ymm0, %ymm1
   %ymm0 = VXORPDZ256rr                         %ymm0, %ymm1                                   
   ; CHECK: %ymm0 = VXORPSYrm                   %ymm0, %rip, 1, _, %rax, _
   %ymm0 = VXORPSZ256rm                         %ymm0, %rip, 1, _, %rax, _                     
   ; CHECK: %ymm0 = VXORPSYrr                   %ymm0, %ymm1
body: |
   ; CHECK: %ymm0 = VPMOVZXWDYrm                %rip, 1, _, %rax, _
   %ymm0 = VPMOVZXWDZ256rm                      %rip, 1, _, %rax, _                            
   ; CHECK: %ymm0 = VPMOVZXWDYrr                %xmm0
   %ymm0 = VPMOVZXWDZ256rr                      %xmm0                                          
   ; CHECK: %ymm0 = VPMOVZXWQYrm                %rip, 1, _, %rax, _
   %ymm0 = VPMOVZXWQZ256rm                      %rip, 1, _, %rax, _                            
   ; CHECK: %ymm0 = VPMOVZXWQYrr                %xmm0                                      
   %ymm0 = VPMOVZXWQZ256rr                      %xmm0                                                 
+  ; CHECK: %ymm0 = VBROADCASTF128              %rip, 1, _, %rax, _
+  %ymm0 = VBROADCASTF32X4Z256rm                %rip, 1, _, %rax, _
+  ; CHECK: %ymm0 = VBROADCASTSDYrm             %rip, 1, _, %rax, _
+  %ymm0 = VBROADCASTF32X2Z256m                 %rip, 1, _, %rax, _
+  ; CHECK: %ymm0 = VBROADCASTSDYrr             %xmm0
+  %ymm0 = VBROADCASTF32X2Z256r                 %xmm0
   ; CHECK: %ymm0 = VBROADCASTSDYrm             %rip, 1, _, %rax, _
   %ymm0 = VBROADCASTSDZ256m                    %rip, 1, _, %rax, _                            
   ; CHECK: %ymm0 = VBROADCASTSDYrr             %xmm0
   %ymm0 = VBROADCASTSDZ256r                    %xmm0                                          
   ; CHECK: %ymm0 = VBROADCASTSSYrm             %rip, 1, _, %rax, _
   %ymm0 = VBROADCASTSSZ256m                    %rip, 1, _, %rax, _                            
   ; CHECK: %ymm0 = VBROADCASTSSYrr             %xmm0
   %ymm0 = VBROADCASTSSZ256r                    %xmm0                                          
   ; CHECK: %ymm0 = VPBROADCASTBYrm             %rip, 1, _, %rax, _
   %ymm0 = VPBROADCASTBZ256m                    %rip, 1, _, %rax, _                            
   ; CHECK: %ymm0 = VPBROADCASTBYrr             %xmm0
   %ymm0 = VPBROADCASTBZ256r                    %xmm0                                          
   ; CHECK: %ymm0 = VPBROADCASTDYrm             %rip, 1, _, %rax, _
   %ymm0 = VPBROADCASTDZ256m                    %rip, 1, _, %rax, _                            
   ; CHECK: %ymm0 = VPBROADCASTDYrr             %xmm0
   %ymm0 = VPBROADCASTDZ256r                    %xmm0                                          
   ; CHECK: %ymm0 = VPBROADCASTWYrm             %rip, 1, _, %rax, _
   %ymm0 = VPBROADCASTWZ256m                    %rip, 1, _, %rax, _                            
   ; CHECK: %ymm0 = VPBROADCASTWYrr             %xmm0
   %ymm0 = VPBROADCASTWZ256r                    %xmm0                                          
+  ; CHECK: %ymm0 = VBROADCASTI128              %rip, 1, _, %rax, _
+  %ymm0 = VBROADCASTI32X4Z256rm                %rip, 1, _, %rax, _
+  ; CHECK: %ymm0 = VPBROADCASTQYrm             %rip, 1, _, %rax, _
+  %ymm0 = VBROADCASTI32X2Z256m                 %rip, 1, _, %rax, _
+  ; CHECK: %ymm0 = VPBROADCASTQYrr             %xmm0
+  %ymm0 = VBROADCASTI32X2Z256r                 %xmm0
   ; CHECK: %ymm0 = VPBROADCASTQYrm             %rip, 1, _, %rax, _  
   %ymm0 = VPBROADCASTQZ256m                    %rip, 1, _, %rax, _                            
   ; CHECK: %ymm0 = VPBROADCASTQYrr             %xmm0                                      
   %ymm0 = VPBROADCASTQZ256r                    %xmm0                                               
   ; CHECK: %ymm0 = VPABSBYrm                   %rip, 1, _, %rax, _
   %ymm0 = VPABSBZ256rm                         %rip, 1, _, %rax, _                            
   ; CHECK: %ymm0 = VPABSBYrr                   %ymm0
   %ymm0 = VPABSBZ256rr                         %ymm0                                          
body: |
   ; CHECK: %xmm0 = VMAXCPDrm                   %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMAXCPDZ128rm                        %xmm0, %rip, 1, _, %rax, _                          
   ; CHECK: %xmm0 = VMAXCPDrr                   %xmm0, %xmm1  
   %xmm0 = VMAXCPDZ128rr                        %xmm0, %xmm1                                        
   ; CHECK: %xmm0 = VMAXCPSrm                   %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMAXCPSZ128rm                        %xmm0, %rip, 1, _, %rax, _                          
   ; CHECK: %xmm0 = VMAXCPSrr                   %xmm0, %xmm1
   %xmm0 = VMAXCPSZ128rr                        %xmm0, %xmm1                                        
-  ; CHECK: %xmm0 = VMAXPDrm                    %xmm0, %rip, 1, _, %rax, _
+  ; CHECK: %xmm0 = VMAXCPDrm                   %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMAXPDZ128rm                         %xmm0, %rip, 1, _, %rax, _                          
-  ; CHECK: %xmm0 = VMAXPDrr                    %xmm0, %xmm1
+  ; CHECK: %xmm0 = VMAXCPDrr                   %xmm0, %xmm1
   %xmm0 = VMAXPDZ128rr                         %xmm0, %xmm1                                        
-  ; CHECK: %xmm0 = VMAXPSrm                    %xmm0, %rip, 1, _, %rax, _
+  ; CHECK: %xmm0 = VMAXCPSrm                   %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMAXPSZ128rm                         %xmm0, %rip, 1, _, %rax, _                          
-  ; CHECK: %xmm0 = VMAXPSrr                    %xmm0, %xmm1
+  ; CHECK: %xmm0 = VMAXCPSrr                   %xmm0, %xmm1
   %xmm0 = VMAXPSZ128rr                         %xmm0, %xmm1                                        
   ; CHECK: %xmm0 = VMINCPDrm                   %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMINCPDZ128rm                        %xmm0, %rip, 1, _, %rax, _                          
   ; CHECK: %xmm0 = VMINCPDrr                   %xmm0, %xmm1  
   %xmm0 = VMINCPDZ128rr                        %xmm0, %xmm1                                        
   ; CHECK: %xmm0 = VMINCPSrm                   %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMINCPSZ128rm                        %xmm0, %rip, 1, _, %rax, _                          
   ; CHECK: %xmm0 = VMINCPSrr                   %xmm0, %xmm1
   %xmm0 = VMINCPSZ128rr                        %xmm0, %xmm1                                        
-  ; CHECK: %xmm0 = VMINPDrm                    %xmm0, %rip, 1, _, %rax, _
+  ; CHECK: %xmm0 = VMINCPDrm                   %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMINPDZ128rm                         %xmm0, %rip, 1, _, %rax, _                          
-  ; CHECK: %xmm0 = VMINPDrr                    %xmm0, %xmm1
+  ; CHECK: %xmm0 = VMINCPDrr                   %xmm0, %xmm1
   %xmm0 = VMINPDZ128rr                         %xmm0, %xmm1                                        
-  ; CHECK: %xmm0 = VMINPSrm                    %xmm0, %rip, 1, _, %rax, _
+  ; CHECK: %xmm0 = VMINCPSrm                   %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMINPSZ128rm                         %xmm0, %rip, 1, _, %rax, _                          
-  ; CHECK: %xmm0 = VMINPSrr                    %xmm0, %xmm1
+  ; CHECK: %xmm0 = VMINCPSrr                   %xmm0, %xmm1
   %xmm0 = VMINPSZ128rr                         %xmm0, %xmm1                                        
   ; CHECK: %xmm0 = VMULPDrm                    %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMULPDZ128rm                         %xmm0, %rip, 1, _, %rax, _                          
   ; CHECK: %xmm0 = VMULPDrr                    %xmm0, %xmm1
   %xmm0 = VMULPDZ128rr                         %xmm0, %xmm1                                        
   ; CHECK: %xmm0 = VMULPSrm                    %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMULPSZ128rm                         %xmm0, %rip, 1, _, %rax, _                          
   ; CHECK: %xmm0 = VMULPSrr                    %xmm0, %xmm1
body: |
   ; CHECK: %xmm0 = VPANDrm                     %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VPANDDZ128rm                         %xmm0, %rip, 1, _, %rax, _                          
   ; CHECK: %xmm0 = VPANDrr                     %xmm0, %xmm1
   %xmm0 = VPANDDZ128rr                         %xmm0, %xmm1                                        
   ; CHECK: %xmm0 = VPANDrm                     %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VPANDQZ128rm                         %xmm0, %rip, 1, _, %rax, _                          
   ; CHECK: %xmm0 = VPANDrr                     %xmm0, %xmm1  
   %xmm0 = VPANDQZ128rr                         %xmm0, %xmm1                                        
+  ; CHECK: %xmm0 = VPANDNrm                    %xmm0, %rip, 1, _, %rax, _
+  %xmm0 = VPANDNDZ128rm                        %xmm0, %rip, 1, _, %rax, _                          
+  ; CHECK: %xmm0 = VPANDNrr                    %xmm0, %xmm1
+  %xmm0 = VPANDNDZ128rr                        %xmm0, %xmm1                                        
+  ; CHECK: %xmm0 = VPANDNrm                    %xmm0, %rip, 1, _, %rax, _
+  %xmm0 = VPANDNQZ128rm                        %xmm0, %rip, 1, _, %rax, _                          
+  ; CHECK: %xmm0 = VPANDNrr                    %xmm0, %xmm1  
+  %xmm0 = VPANDNQZ128rr                        %xmm0, %xmm1                                        
   ; CHECK: %xmm0 = VPAVGBrm                    %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VPAVGBZ128rm                         %xmm0, %rip, 1, _, %rax, _                          
   ; CHECK: %xmm0 = VPAVGBrr                    %xmm0, %xmm1  
   %xmm0 = VPAVGBZ128rr                         %xmm0, %xmm1                                        
   ; CHECK: %xmm0 = VPAVGWrm                    %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VPAVGWZ128rm                         %xmm0, %rip, 1, _, %rax, _                          
   ; CHECK: %xmm0 = VPAVGWrr                    %xmm0, %xmm1
   %xmm0 = VPAVGWZ128rr                         %xmm0, %xmm1                                        
body: |
   ; CHECK: %xmm0 = VPBROADCASTQrm              %rip, _, _, _, _
   %xmm0 = VPBROADCASTQZ128m                    %rip, _, _, _, _                                    
   ; CHECK: %xmm0 = VPBROADCASTQrr              %xmm0
   %xmm0 = VPBROADCASTQZ128r                    %xmm0                                               
   ; CHECK: %xmm0 = VPBROADCASTWrm              %rip, _, _, _, _ 
   %xmm0 = VPBROADCASTWZ128m                    %rip, _, _, _, _                                    
   ; CHECK: %xmm0 = VPBROADCASTWrr              %xmm0                                   
   %xmm0 = VPBROADCASTWZ128r                    %xmm0                                                                                             
+  ; CHECK: %xmm0 = VPBROADCASTQrm              %rip, _, _, _, _
+  %xmm0 = VBROADCASTI32X2Z128m                 %rip, _, _, _, _
+  ; CHECK: %xmm0 = VPBROADCASTQrr              %xmm0
+  %xmm0 = VBROADCASTI32X2Z128r                 %xmm0
   ; CHECK: %xmm0 = VCVTPS2PHrr                 %xmm0, 2
   %xmm0 = VCVTPS2PHZ128rr                      %xmm0, 2                                            
   ; CHECK: VCVTPS2PHmr                         %rdi, %xmm0, 1, _, 0, _, _              
   VCVTPS2PHZ128mr                              %rdi, %xmm0, 1, _, 0, _, _                                               
   ; CHECK: %xmm0 = VPABSBrm                    %rip, 1, _, %rax, _
   %xmm0 = VPABSBZ128rm                         %rip, 1, _, %rax, _                                 
   ; CHECK: %xmm0 = VPABSBrr                    %xmm0
   %xmm0 = VPABSBZ128rr                         %xmm0                                               
body: |
   ; CHECK: %xmm0 = VMAXCSDrm                   %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMAXCSDZrm                           %xmm0, %rip, 1, _, %rax, _                              
   ; CHECK: %xmm0 = VMAXCSDrr                   %xmm0, %xmm1
   %xmm0 = VMAXCSDZrr                           %xmm0, %xmm1                                            
   ; CHECK: %xmm0 = VMAXCSSrm                   %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMAXCSSZrm                           %xmm0, %rip, 1, _, %rax, _                              
   ; CHECK: %xmm0 = VMAXCSSrr                   %xmm0, %xmm1
   %xmm0 = VMAXCSSZrr                           %xmm0, %xmm1                                            
-  ; CHECK: %xmm0 = VMAXSDrm                    %xmm0, %rip, 1, _, %rax, _
+  ; CHECK: %xmm0 = VMAXCSDrm                   %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMAXSDZrm                            %xmm0, %rip, 1, _, %rax, _                              
   ; CHECK: %xmm0 = VMAXSDrm_Int                %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMAXSDZrm_Int                        %xmm0, %rip, 1, _, %rax, _                              
-  ; CHECK: %xmm0 = VMAXSDrr                    %xmm0, %xmm1
+  ; CHECK: %xmm0 = VMAXCSDrr                   %xmm0, %xmm1
   %xmm0 = VMAXSDZrr                            %xmm0, %xmm1                                            
   ; CHECK: %xmm0 = VMAXSDrr_Int                %xmm0, %xmm1
   %xmm0 = VMAXSDZrr_Int                        %xmm0, %xmm1                                            
-  ; CHECK: %xmm0 = VMAXSSrm                    %xmm0, %rip, 1, _, %rax, _
+  ; CHECK: %xmm0 = VMAXCSSrm                   %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMAXSSZrm                            %xmm0, %rip, 1, _, %rax, _                              
   ; CHECK: %xmm0 = VMAXSSrm_Int                %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMAXSSZrm_Int                        %xmm0, %rip, 1, _, %rax, _                              
-  ; CHECK: %xmm0 = VMAXSSrr                    %xmm0, %xmm1
+  ; CHECK: %xmm0 = VMAXCSSrr                   %xmm0, %xmm1
   %xmm0 = VMAXSSZrr                            %xmm0, %xmm1                                            
   ; CHECK: %xmm0 = VMAXSSrr_Int                %xmm0, %xmm1
   %xmm0 = VMAXSSZrr_Int                        %xmm0, %xmm1                                            
   ; CHECK: %xmm0 = VMINCSDrm                   %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMINCSDZrm                           %xmm0, %rip, 1, _, %rax, _                              
   ; CHECK: %xmm0 = VMINCSDrr                   %xmm0, %xmm1
   %xmm0 = VMINCSDZrr                           %xmm0, %xmm1                                            
   ; CHECK: %xmm0 = VMINCSSrm                   %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMINCSSZrm                           %xmm0, %rip, 1, _, %rax, _                              
   ; CHECK: %xmm0 = VMINCSSrr                   %xmm0, %xmm1
   %xmm0 = VMINCSSZrr                           %xmm0, %xmm1                                            
-  ; CHECK: %xmm0 = VMINSDrm                    %xmm0, %rip, 1, _, %rax, _
+  ; CHECK: %xmm0 = VMINCSDrm                   %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMINSDZrm                            %xmm0, %rip, 1, _, %rax, _                              
   ; CHECK: %xmm0 = VMINSDrm_Int                %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMINSDZrm_Int                        %xmm0, %rip, 1, _, %rax, _                              
-  ; CHECK: %xmm0 = VMINSDrr                    %xmm0, %xmm1
+  ; CHECK: %xmm0 = VMINCSDrr                   %xmm0, %xmm1
   %xmm0 = VMINSDZrr                            %xmm0, %xmm1                                            
   ; CHECK: %xmm0 = VMINSDrr_Int                %xmm0, %xmm1
   %xmm0 = VMINSDZrr_Int                        %xmm0, %xmm1                                            
-  ; CHECK: %xmm0 = VMINSSrm                    %xmm0, %rip, 1, _, %rax, _
+  ; CHECK: %xmm0 = VMINCSSrm                   %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMINSSZrm                            %xmm0, %rip, 1, _, %rax, _                              
   ; CHECK: %xmm0 = VMINSSrm_Int                %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMINSSZrm_Int                        %xmm0, %rip, 1, _, %rax, _                              
-  ; CHECK: %xmm0 = VMINSSrr                    %xmm0, %xmm1
+  ; CHECK: %xmm0 = VMINCSSrr                   %xmm0, %xmm1
   %xmm0 = VMINSSZrr                            %xmm0, %xmm1                                            
   ; CHECK: %xmm0 = VMINSSrr_Int                %xmm0, %xmm1
   %xmm0 = VMINSSZrr_Int                        %xmm0, %xmm1                                            
   ; CHECK: %xmm0 = VMULSDrm                    %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMULSDZrm                            %xmm0, %rip, 1, _, %rax, _                              
   ; CHECK: %xmm0 = VMULSDrm_Int                %xmm0, %rip, 1, _, %rax, _
   %xmm0 = VMULSDZrm_Int                        %xmm0, %rip, 1, _, %rax, _                              
   ; CHECK: %xmm0 = VMULSDrr                    %xmm0, %xmm1
body: |
   ; CHECK: VPEXTRQmr                           %rdi, 1, _, 0, _, %xmm0, 3       
   VPEXTRQZmr                                   %rdi, 1, _, 0, _, %xmm0, 3                              
   ; CHECK: %rax = VPEXTRQrr                    %xmm0, 1      
   %rax = VPEXTRQZrr                            %xmm0, 1                                                
   ; CHECK: VPEXTRWmr                           %rdi, 1, _, 0, _,  %xmm0, 3       
   VPEXTRWZmr                                   %rdi, 1, _, 0, _,  %xmm0, 3                             
   ; CHECK: %eax = VPEXTRWri                    %xmm0, 1                                                     
   %eax = VPEXTRWZrr                            %xmm0, 1                                                    
+  ; CHECK: %eax = VPEXTRWrr_REV               %xmm0, 1      
+  %eax = VPEXTRWZrr_REV                        %xmm0, 1                                                     
   ; CHECK: %xmm0 = VPINSRBrm                   %xmm0, %rsi, 1, _, 0, _, 3      
   %xmm0 = VPINSRBZrm                           %xmm0, %rsi, 1, _, 0, _, 3                              
   ; CHECK: %xmm0 = VPINSRBrr                   %xmm0, %edi, 5      
   %xmm0 = VPINSRBZrr                           %xmm0, %edi, 5                                          
   ; CHECK: %xmm0 = VPINSRDrm                   %xmm0, %rsi, 1, _, 0, _, 3      
   %xmm0 = VPINSRDZrm                           %xmm0, %rsi, 1, _, 0, _, 3                              
   ; CHECK: %xmm0 = VPINSRDrr                   %xmm0, %edi, 5            
   %xmm0 = VPINSRDZrr                           %xmm0, %edi, 5                                          
body: |
   ; CHECK: %xmm0 = VSQRTSSm                    %xmm0, _, _, _, _, _
   %xmm0 = VSQRTSSZm                            %xmm0, _, _, _, _, _                                    
   ; CHECK: %xmm0 = VSQRTSSm_Int                %xmm0, _, _, _, _, _
   %xmm0 = VSQRTSSZm_Int                        %xmm0, _, _, _, _, _                                    
   ; CHECK: %xmm0 = VSQRTSSr                    %xmm0, _
   %xmm0 = VSQRTSSZr                            %xmm0, _                                                
   ; CHECK: %xmm0 = VSQRTSSr_Int                %xmm0, _                                              
   %xmm0 = VSQRTSSZr_Int                        %xmm0, _                                                
-  ; CHECK: %rdi = VCVTSD2SI64rm                %rdi, %xmm0, 1, _, 0
-  %rdi = VCVTSD2SI64Zrm                        %rdi, %xmm0, 1, _, 0                                    
   ; CHECK: %rdi = VCVTSD2SI64rr                %xmm0
   %rdi = VCVTSD2SI64Zrr                        %xmm0                                                   
-  ; CHECK: %edi = VCVTSD2SIrm                  %rdi, %xmm0, 1, _, 0
-  %edi = VCVTSD2SIZrm                          %rdi, %xmm0, 1, _, 0                                    
   ; CHECK: %edi = VCVTSD2SIrr                  %xmm0
   %edi = VCVTSD2SIZrr                          %xmm0                                                   
   ; CHECK: %xmm0 = VCVTSD2SSrm                 %xmm0, %rdi, 1, _, 0, _
   %xmm0 = VCVTSD2SSZrm                         %xmm0, %rdi, 1, _, 0, _                                 
   ; CHECK: %xmm0 = VCVTSD2SSrr                 %xmm0, _
   %xmm0 = VCVTSD2SSZrr                         %xmm0, _                                                
   ; CHECK: %xmm0 = VCVTSI2SDrm                 %xmm0, %rdi, 1, _, 0, _
   %xmm0 = VCVTSI2SDZrm                         %xmm0, %rdi, 1, _, 0, _                                 
   ; CHECK: %xmm0 = Int_VCVTSI2SDrm             %xmm0, %rdi, 1, _, 0, _
   %xmm0 = VCVTSI2SDZrm_Int                     %xmm0, %rdi, 1, _, 0, _                                 
   ; CHECK: %xmm0 = VCVTSI2SDrr                 %xmm0, _
   %xmm0 = VCVTSI2SDZrr                         %xmm0, _                                                
   ; CHECK: %xmm0 = Int_VCVTSI2SDrr             %xmm0, _
   %xmm0 = VCVTSI2SDZrr_Int                     %xmm0, _                                                
   ; CHECK: %xmm0 = VCVTSI2SSrm                 %xmm0, %rdi, 1, _, 0, _
   %xmm0 = VCVTSI2SSZrm                         %xmm0, %rdi, 1, _, 0, _                                 
   ; CHECK: %xmm0 = Int_VCVTSI2SSrm             %xmm0, %rdi, 1, _, 0, _
   %xmm0 = VCVTSI2SSZrm_Int                     %xmm0, %rdi, 1, _, 0, _                                 
   ; CHECK: %xmm0 = VCVTSI2SSrr                 %xmm0, _
   %xmm0 = VCVTSI2SSZrr                         %xmm0, _                                                
   ; CHECK: %xmm0 = Int_VCVTSI2SSrr             %xmm0, _
   %xmm0 = VCVTSI2SSZrr_Int                     %xmm0, _                                                
+  ; CHECK: %xmm0 = VCVTSI2SD64rm               %xmm0, %rdi, 1, _, 0, _
+  %xmm0 = VCVTSI642SDZrm                       %xmm0, %rdi, 1, _, 0, _
+  ; CHECK: %xmm0 = Int_VCVTSI2SD64rm           %xmm0, %rdi, 1, _, 0, _
+  %xmm0 = VCVTSI642SDZrm_Int                   %xmm0, %rdi, 1, _, 0, _
+  ; CHECK: %xmm0 = VCVTSI2SD64rr               %xmm0, _
+  %xmm0 = VCVTSI642SDZrr                       %xmm0, _
+  ; CHECK: %xmm0 = Int_VCVTSI2SD64rr           %xmm0, _
+  %xmm0 = VCVTSI642SDZrr_Int                   %xmm0, _
+  ; CHECK: %xmm0 = VCVTSI2SS64rm               %xmm0, %rdi, 1, _, 0, _ 
+  %xmm0 = VCVTSI642SSZrm                       %xmm0, %rdi, 1, _, 0, _
+  ; CHECK: %xmm0 = Int_VCVTSI2SS64rm           %xmm0, %rdi, 1, _, 0, _
+  %xmm0 = VCVTSI642SSZrm_Int                   %xmm0, %rdi, 1, _, 0, _
+  ; CHECK: %xmm0 = VCVTSI2SS64rr               %xmm0, _ 
+  %xmm0 = VCVTSI642SSZrr                       %xmm0, _
+  ; CHECK: %xmm0 = Int_VCVTSI2SS64rr           %xmm0, _
+  %xmm0 = VCVTSI642SSZrr_Int                   %xmm0, _
   ; CHECK: %xmm0 = VCVTSS2SDrm                 %xmm0, %rdi, 1, _, 0, _
   %xmm0 = VCVTSS2SDZrm                         %xmm0, %rdi, 1, _, 0, _                                 
   ; CHECK: %xmm0 = VCVTSS2SDrr                 %xmm0, _
   %xmm0 = VCVTSS2SDZrr                         %xmm0, _                                                
-  ; CHECK: %rdi = VCVTSS2SI64rm                %rdi, %xmm0, 1, _, 0
-  %rdi = VCVTSS2SI64Zrm                        %rdi, %xmm0, 1, _, 0                                    
   ; CHECK: %rdi = VCVTSS2SI64rr                %xmm0
   %rdi = VCVTSS2SI64Zrr                        %xmm0                                                   
-  ; CHECK: %edi = VCVTSS2SIrm                  %rdi, %xmm0, 1, _, 0
-  %edi = VCVTSS2SIZrm                          %rdi, %xmm0, 1, _, 0                                    
   ; CHECK: %edi = VCVTSS2SIrr                  %xmm0
   %edi = VCVTSS2SIZrr                          %xmm0                                                   
   ; CHECK: %rdi = VCVTTSD2SI64rm               %rdi, %xmm0, 1, _, 0
   %rdi = VCVTTSD2SI64Zrm                       %rdi, %xmm0, 1, _, 0                                    
   ; CHECK: %rdi = Int_VCVTTSD2SI64rm           %rdi, %xmm0, 1, _, 0
   %rdi = VCVTTSD2SI64Zrm_Int                   %rdi, %xmm0, 1, _, 0                                    
   ; CHECK: %rdi = VCVTTSD2SI64rr               %xmm0
   %rdi = VCVTTSD2SI64Zrr                       %xmm0                                                   
body: |
   ; CHECK: %xmm0 = VMOVDI2SSrr                 %eax
   %xmm0 = VMOVDI2SSZrr                         %eax                                                    
   ; CHECK: VMOVSDmr                            %rdi, %xmm0, _, _, _, _
   VMOVSDZmr                                    %rdi, %xmm0, _, _, _, _                                 
   ; CHECK: %xmm0 = VMOVSDrm                    %rip, _, _, _, _
   %xmm0 = VMOVSDZrm                            %rip, _, _, _, _                                        
   ; CHECK: %xmm0 = VMOVSDrr                    %xmm0, _
   %xmm0 = VMOVSDZrr                            %xmm0, _                                                
+  ; CHECK: %xmm0 = VMOVSDrr_REV                %xmm0, _
+  %xmm0 = VMOVSDZrr_REV                        %xmm0, _                                                
+  ; CHECK: %rax = VMOVSDto64rr                 %xmm0
+  %rax = VMOVSDto64Zrr                         %xmm0
+  ; CHECK: VMOVSDto64mr                        %rdi, %xmm0, _, _, _, _
+  VMOVSDto64Zmr                                %rdi, %xmm0, _, _, _, _
   ; CHECK: VMOVSSmr                            %rdi, %xmm0, _, _, _, _
   VMOVSSZmr                                    %rdi, %xmm0, _, _, _, _                                 
   ; CHECK: %xmm0 = VMOVSSrm                    %rip, _, _, _, _
   %xmm0 = VMOVSSZrm                            %rip, _, _, _, _                                        
   ; CHECK: %xmm0 = VMOVSSrr                    %xmm0, _
   %xmm0 = VMOVSSZrr                            %xmm0, _                                                
   ; CHECK: %xmm0 = VMOVSSrr_REV                %xmm0, _
   %xmm0 = VMOVSSZrr_REV                        %xmm0, _                                                
+  ; CHECK: VMOVSS2DImr                         %rdi, %xmm0, _, _, _, _
+  VMOVSS2DIZmr                                 %rdi, %xmm0, _, _, _, _
+  ; CHECK: %eax = VMOVSS2DIrr                  %xmm0
+  %eax = VMOVSS2DIZrr                          %xmm0
   ; CHECK: %xmm0 = VMOV64toPQIrr               %rdi
   %xmm0 = VMOV64toPQIZrr                       %rdi                                                    
+  ; CHECK: %xmm0 = VMOV64toPQIrm               %rdi, _, _, _, _
+  %xmm0 = VMOV64toPQIZrm                       %rdi, _, _, _, _
   ; CHECK: %xmm0 = VMOV64toSDrr                %rdi 
   %xmm0 = VMOV64toSDZrr                        %rdi                                                    
   ; CHECK: %xmm0 = VMOVDI2PDIrm                %rip, _, _, _, _
   %xmm0 = VMOVDI2PDIZrm                        %rip, _, _, _, _                                        
   ; CHECK: %xmm0 = VMOVDI2PDIrr                %edi
   %xmm0 = VMOVDI2PDIZrr                        %edi                                                    
   ; CHECK: %xmm0 = VMOVLHPSrr                  %xmm0, _
   %xmm0 = VMOVLHPSZrr                          %xmm0, _                                                
   ; CHECK: %xmm0 = VMOVHLPSrr                  %xmm0, _
   %xmm0 = VMOVHLPSZrr                          %xmm0, _                                                
   ; CHECK: VMOVPDI2DImr                        %rdi, %xmm0, _, _, _, _
   VMOVPDI2DIZmr                                %rdi, %xmm0, _, _, _, _                                 
   ; CHECK: %edi = VMOVPDI2DIrr                 %xmm0
-  %edi = VMOVPDI2DIZrr                         %xmm0                                                   
+  %edi = VMOVPDI2DIZrr                         %xmm0
+  ; CHECK: %xmm0 = VMOVPQI2QIrr                %xmm0
+  %xmm0 = VMOVPQI2QIZrr                        %xmm0
   ; CHECK: VMOVPQI2QImr                        %rdi, %xmm0, _, _, _, _
   VMOVPQI2QIZmr                                %rdi, %xmm0, _, _, _, _                                 
   ; CHECK: %rdi = VMOVPQIto64rr                %xmm0
   %rdi = VMOVPQIto64Zrr                        %xmm0                                                   
+  ; CHECK: VMOVPQIto64mr                       %rdi, %xmm0, _, _, _, _
+  VMOVPQIto64Zmr                               %rdi, %xmm0, _, _, _, _
   ; CHECK: %xmm0 = VMOVQI2PQIrm                %rip, _, _, _, _
   %xmm0 = VMOVQI2PQIZrm                        %rip, _, _, _, _                                        
   ; CHECK: %xmm0 = VMOVZPQILo2PQIrr            %xmm0                                               
   %xmm0 = VMOVZPQILo2PQIZrr                    %xmm0                                                   
   ; CHECK: Int_VCOMISDrm                       %xmm0, %rdi, _, _, _, _, implicit-def %eflags
   Int_VCOMISDZrm                               %xmm0, %rdi, _, _, _, _, implicit-def %eflags           
   ; CHECK: Int_VCOMISDrr                       %xmm0, %xmm1, implicit-def %eflags  
   Int_VCOMISDZrr                               %xmm0, %xmm1, implicit-def %eflags                      
body: |
   ; CHECK: VUCOMISDrm                          %xmm0, %rdi, _, _, _, _, implicit-def %eflags
   VUCOMISDZrm                                  %xmm0, %rdi, _, _, _, _, implicit-def %eflags           
   ; CHECK: VUCOMISDrr                          %xmm0, %xmm1, implicit-def %eflags 
   VUCOMISDZrr                                  %xmm0, %xmm1, implicit-def %eflags                      
   ; CHECK: VUCOMISSrm                          %xmm0, %rdi, _, _, _, _, implicit-def %eflags 
   VUCOMISSZrm                                  %xmm0, %rdi, _, _, _, _, implicit-def %eflags           
   ; CHECK: VUCOMISSrr                          %xmm0, %xmm1, implicit-def %eflags 
   VUCOMISSZrr                                  %xmm0, %xmm1, implicit-def %eflags 
+  ; CHECK: VEXTRACTPSmr                        %rdi, 1, _, 0, _, %xmm0, _
+  VEXTRACTPSZmr                                %rdi, 1, _, 0, _, %xmm0, _
+  ; CHECK: %eax = VEXTRACTPSrr                 %xmm0, _
+  %eax = VEXTRACTPSZrr                         %xmm0, _
+  ; CHECK: %xmm0 = VINSERTPSrm                 %xmm0, %rdi, _, _, _, _, _
+  %xmm0 = VINSERTPSZrm                         %xmm0, %rdi, _, _, _, _, _
+  ; CHECK: %xmm0 = VINSERTPSrr                 %xmm0, %xmm0, _ 
+  %xmm0 = VINSERTPSZrr                         %xmm0, %xmm0, _
 
   RET 0, %zmm0, %zmm1                          
 ...
 ---
   # CHECK-LABEL: name: evex_z256_to_evex_test
   # CHECK: bb.0:
 
 name: evex_z256_to_evex_test
body: |
   ; CHECK: %ymm16 = VPANDDZ256rm               %ymm16, %rip, 1, _, %rax, _
   %ymm16 = VPANDDZ256rm                        %ymm16, %rip, 1, _, %rax, _                   
   ; CHECK: %ymm16 = VPANDDZ256rr               %ymm16, %ymm1  
   %ymm16 = VPANDDZ256rr                        %ymm16, %ymm1                                 
   ; CHECK: %ymm16 = VPANDQZ256rm               %ymm16, %rip, 1, _, %rax, _
   %ymm16 = VPANDQZ256rm                        %ymm16, %rip, 1, _, %rax, _                   
   ; CHECK: %ymm16 = VPANDQZ256rr               %ymm16, %ymm1
   %ymm16 = VPANDQZ256rr                        %ymm16, %ymm1                                 
+  ; CHECK: %ymm16 = VPANDNDZ256rm               %ymm16, %rip, 1, _, %rax, _
+  %ymm16 = VPANDNDZ256rm                        %ymm16, %rip, 1, _, %rax, _                   
+  ; CHECK: %ymm16 = VPANDNDZ256rr               %ymm16, %ymm1  
+  %ymm16 = VPANDNDZ256rr                        %ymm16, %ymm1                                 
+  ; CHECK: %ymm16 = VPANDNQZ256rm               %ymm16, %rip, 1, _, %rax, _
+  %ymm16 = VPANDNQZ256rm                        %ymm16, %rip, 1, _, %rax, _                   
+  ; CHECK: %ymm16 = VPANDNQZ256rr               %ymm16, %ymm1
+  %ymm16 = VPANDNQZ256rr                        %ymm16, %ymm1                                 
   ; CHECK: %ymm16 = VPAVGBZ256rm               %ymm16, %rip, 1, _, %rax, _
   %ymm16 = VPAVGBZ256rm                        %ymm16, %rip, 1, _, %rax, _                   
   ; CHECK: %ymm16 = VPAVGBZ256rr               %ymm16, %ymm1
   %ymm16 = VPAVGBZ256rr                        %ymm16, %ymm1                                 
   ; CHECK: %ymm16 = VPAVGWZ256rm               %ymm16, %rip, 1, _, %rax, _
   %ymm16 = VPAVGWZ256rm                        %ymm16, %rip, 1, _, %rax, _                   
   ; CHECK: %ymm16 = VPAVGWZ256rr               %ymm16, %ymm1
   %ymm16 = VPAVGWZ256rr                        %ymm16, %ymm1                                 
body: |
   ; CHECK: %ymm16 = VPMOVZXWDZ256rm            %rip, 1, _, %rax, _
   %ymm16 = VPMOVZXWDZ256rm                     %rip, 1, _, %rax, _                           
   ; CHECK: %ymm16 = VPMOVZXWDZ256rr            %xmm0
   %ymm16 = VPMOVZXWDZ256rr                     %xmm0                                         
   ; CHECK: %ymm16 = VPMOVZXWQZ256rm            %rip, 1, _, %rax, _
   %ymm16 = VPMOVZXWQZ256rm                     %rip, 1, _, %rax, _                           
   ; CHECK: %ymm16 = VPMOVZXWQZ256rr            %xmm0    
   %ymm16 = VPMOVZXWQZ256rr                     %xmm0                                                 
+  ; CHECK: %ymm16 = VBROADCASTF32X2Z256m       %rip, 1, _, %rax, _
+  %ymm16 = VBROADCASTF32X2Z256m                %rip, 1, _, %rax, _
+  ; CHECK: %ymm16 = VBROADCASTF32X2Z256r       %xmm16
+  %ymm16 = VBROADCASTF32X2Z256r                %xmm16
+  ; CHECK: %ymm16 = VBROADCASTF32X4Z256rm      %rip, 1, _, %rax, _
+  %ymm16 = VBROADCASTF32X4Z256rm               %rip, 1, _, %rax, _
   ; CHECK: %ymm16 = VBROADCASTSDZ256m          %rip, 1, _, %rax, _
   %ymm16 = VBROADCASTSDZ256m                   %rip, 1, _, %rax, _                           
   ; CHECK: %ymm16 = VBROADCASTSDZ256r          %xmm0
   %ymm16 = VBROADCASTSDZ256r                   %xmm0                                         
   ; CHECK: %ymm16 = VBROADCASTSSZ256m          %rip, 1, _, %rax, _
   %ymm16 = VBROADCASTSSZ256m                   %rip, 1, _, %rax, _                           
   ; CHECK: %ymm16 = VBROADCASTSSZ256r          %xmm0
   %ymm16 = VBROADCASTSSZ256r                   %xmm0                                         
   ; CHECK: %ymm16 = VPBROADCASTBZ256m          %rip, 1, _, %rax, _
   %ymm16 = VPBROADCASTBZ256m                   %rip, 1, _, %rax, _                           
   ; CHECK: %ymm16 = VPBROADCASTBZ256r          %xmm0
   %ymm16 = VPBROADCASTBZ256r                   %xmm0                                         
   ; CHECK: %ymm16 = VPBROADCASTDZ256m          %rip, 1, _, %rax, _
   %ymm16 = VPBROADCASTDZ256m                   %rip, 1, _, %rax, _                           
   ; CHECK: %ymm16 = VPBROADCASTDZ256r          %xmm0
   %ymm16 = VPBROADCASTDZ256r                   %xmm0                                         
   ; CHECK: %ymm16 = VPBROADCASTWZ256m          %rip, 1, _, %rax, _
   %ymm16 = VPBROADCASTWZ256m                   %rip, 1, _, %rax, _                           
   ; CHECK: %ymm16 = VPBROADCASTWZ256r          %xmm0
   %ymm16 = VPBROADCASTWZ256r                   %xmm0                                         
+  ; CHECK: %ymm16 = VBROADCASTI32X4Z256rm      %rip, 1, _, %rax, _
+  %ymm16 = VBROADCASTI32X4Z256rm               %rip, 1, _, %rax, _
+  ; CHECK: %ymm16 = VBROADCASTI32X2Z256m       %rip, 1, _, %rax, _
+  %ymm16 = VBROADCASTI32X2Z256m                %rip, 1, _, %rax, _
+  ; CHECK: %ymm16 = VBROADCASTI32X2Z256r       %xmm16
+  %ymm16 = VBROADCASTI32X2Z256r                %xmm16
   ; CHECK: %ymm16 = VPBROADCASTQZ256m          %rip, 1, _, %rax, _  
   %ymm16 = VPBROADCASTQZ256m                   %rip, 1, _, %rax, _                           
   ; CHECK: %ymm16 = VPBROADCASTQZ256r          %xmm0  
   %ymm16 = VPBROADCASTQZ256r                   %xmm0                                               
   ; CHECK: %ymm16 = VPABSBZ256rm               %rip, 1, _, %rax, _
   %ymm16 = VPABSBZ256rm                        %rip, 1, _, %rax, _                           
   ; CHECK: %ymm16 = VPABSBZ256rr               %ymm16
   %ymm16 = VPABSBZ256rr                        %ymm16                                        
body: |
   ; CHECK: %xmm16 = VPANDDZ128rm               %xmm16, %rip, 1, _, %rax, _
   %xmm16 = VPANDDZ128rm                        %xmm16, %rip, 1, _, %rax, _                               
   ; CHECK: %xmm16 = VPANDDZ128rr               %xmm16, %xmm1
   %xmm16 = VPANDDZ128rr                        %xmm16, %xmm1                                             
   ; CHECK: %xmm16 = VPANDQZ128rm               %xmm16, %rip, 1, _, %rax, _
   %xmm16 = VPANDQZ128rm                        %xmm16, %rip, 1, _, %rax, _                               
   ; CHECK: %xmm16 = VPANDQZ128rr               %xmm16, %xmm1  
   %xmm16 = VPANDQZ128rr                        %xmm16, %xmm1                                             
+  ; CHECK: %xmm16 = VPANDNDZ128rm              %xmm16, %rip, 1, _, %rax, _
+  %xmm16 = VPANDNDZ128rm                       %xmm16, %rip, 1, _, %rax, _                               
+  ; CHECK: %xmm16 = VPANDNDZ128rr              %xmm16, %xmm1
+  %xmm16 = VPANDNDZ128rr                       %xmm16, %xmm1                                             
+  ; CHECK: %xmm16 = VPANDNQZ128rm              %xmm16, %rip, 1, _, %rax, _
+  %xmm16 = VPANDNQZ128rm                       %xmm16, %rip, 1, _, %rax, _                               
+  ; CHECK: %xmm16 = VPANDNQZ128rr              %xmm16, %xmm1  
+  %xmm16 = VPANDNQZ128rr                       %xmm16, %xmm1                                             
   ; CHECK: %xmm16 = VPAVGBZ128rm               %xmm16, %rip, 1, _, %rax, _
   %xmm16 = VPAVGBZ128rm                        %xmm16, %rip, 1, _, %rax, _                               
   ; CHECK: %xmm16 = VPAVGBZ128rr               %xmm16, %xmm1  
   %xmm16 = VPAVGBZ128rr                        %xmm16, %xmm1                                             
   ; CHECK: %xmm16 = VPAVGWZ128rm               %xmm16, %rip, 1, _, %rax, _
   %xmm16 = VPAVGWZ128rm                        %xmm16, %rip, 1, _, %rax, _                               
   ; CHECK: %xmm16 = VPAVGWZ128rr               %xmm16, %xmm1
   %xmm16 = VPAVGWZ128rr                        %xmm16, %xmm1                                             
body: |
   ; CHECK: %xmm16 = VPBROADCASTQZ128m          %rip, _, _, _, _
   %xmm16 = VPBROADCASTQZ128m                   %rip, _, _, _, _                                          
   ; CHECK: %xmm16 = VPBROADCASTQZ128r          %xmm16
   %xmm16 = VPBROADCASTQZ128r                   %xmm16                                                    
   ; CHECK: %xmm16 = VPBROADCASTWZ128m          %rip, _, _, _, _ 
   %xmm16 = VPBROADCASTWZ128m                   %rip, _, _, _, _                                          
   ; CHECK: %xmm16 = VPBROADCASTWZ128r          %xmm16
   %xmm16 = VPBROADCASTWZ128r                   %xmm16                                                                                            
+  ; CHECK: %xmm16 = VBROADCASTI32X2Z128m       %rip, _, _, _, _
+  %xmm16 = VBROADCASTI32X2Z128m                %rip, _, _, _, _
+  ; CHECK: %xmm16 = VBROADCASTI32X2Z128r       %xmm0
+  %xmm16 = VBROADCASTI32X2Z128r                %xmm0
   ; CHECK: %xmm16 = VCVTPS2PHZ128rr            %xmm16, 2
   %xmm16 = VCVTPS2PHZ128rr                     %xmm16, 2                                                 
   ; CHECK: VCVTPS2PHZ128mr                     %rdi, %xmm16, 1, _, 0, _, _  
   VCVTPS2PHZ128mr                              %rdi, %xmm16, 1, _, 0, _, _                                               
   ; CHECK: %xmm16 = VPABSBZ128rm               %rip, 1, _, %rax, _
   %xmm16 = VPABSBZ128rm                        %rip, 1, _, %rax, _                                       
   ; CHECK: %xmm16 = VPABSBZ128rr               %xmm16
   %xmm16 = VPABSBZ128rr                        %xmm16                                                    
   ; CHECK: %xmm16 = VPABSDZ128rm               %rip, 1, _, %rax, _
   %xmm16 = VPABSDZ128rm                        %rip, 1, _, %rax, _                                       
   ; CHECK: %xmm16 = VPABSDZ128rr               %xmm16
   %xmm16 = VPABSDZ128rr                        %xmm16                                                    
   ; CHECK: %xmm16 = VPABSWZ128rm               %rip, 1, _, %rax, _
   %xmm16 = VPABSWZ128rm                        %rip, 1, _, %rax, _                                       
   ; CHECK: %xmm16 = VPABSWZ128rr               %xmm16
   %xmm16 = VPABSWZ128rr                        %xmm16                                                    
   ; CHECK: %xmm16 = VPALIGNRZ128rmi            %xmm16, _, _, _, _, _, _
   %xmm16 = VPALIGNRZ128rmi                     %xmm16, _, _, _, _, _, _                                  
   ; CHECK: %xmm16 = VPALIGNRZ128rri            %xmm16, %xmm1, 15
   %xmm16 = VPALIGNRZ128rri                     %xmm16, %xmm1, 15
+  ; CHECK: VEXTRACTPSZmr                       %rdi, 1, _, 0, _, %xmm16, _
+  VEXTRACTPSZmr                                %rdi, 1, _, 0, _, %xmm16, _
+  ; CHECK: %eax = VEXTRACTPSZrr                %xmm16, _
+  %eax = VEXTRACTPSZrr                         %xmm16, _
+  ; CHECK: %xmm16 = VINSERTPSZrm               %xmm16, %rdi, _, _, _, _, _
+  %xmm16 = VINSERTPSZrm                        %xmm16, %rdi, _, _, _, _, _
+  ; CHECK: %xmm16 = VINSERTPSZrr               %xmm16, %xmm16, _ 
+  %xmm16 = VINSERTPSZrr                        %xmm16, %xmm16, _
     
       RET 0, %zmm0, %zmm1
 ...
 ---
   # CHECK-LABEL: name: evex_scalar_to_evex_test
   # CHECK: bb.0:                               
 
 name: evex_scalar_to_evex_test
body: |
   ; CHECK: VPEXTRQZmr                          %rdi, 1, _, 0, _, %xmm16, 3       
   VPEXTRQZmr                                   %rdi, 1, _, 0, _, %xmm16, 3                                
   ; CHECK: %rax = VPEXTRQZrr                   %xmm16, 1      
   %rax = VPEXTRQZrr                            %xmm16, 1                                                  
   ; CHECK: VPEXTRWZmr                          %rdi, 1, _, 0, _,  %xmm16, 3       
   VPEXTRWZmr                                   %rdi, 1, _, 0, _,  %xmm16, 3                               
   ; CHECK: %eax = VPEXTRWZrr                   %xmm16, 1      
   %eax = VPEXTRWZrr                            %xmm16, 1                                                     
+  ; CHECK: %eax = VPEXTRWZrr_REV               %xmm16, 1      
+  %eax = VPEXTRWZrr_REV                        %xmm16, 1                                                     
   ; CHECK: %xmm16 = VPINSRBZrm                 %xmm16, %rsi, 1, _, 0, _, 3      
   %xmm16 = VPINSRBZrm                          %xmm16, %rsi, 1, _, 0, _, 3                                
   ; CHECK: %xmm16 = VPINSRBZrr                 %xmm16, %edi, 5      
   %xmm16 = VPINSRBZrr                          %xmm16, %edi, 5                                            
   ; CHECK: %xmm16 = VPINSRDZrm                 %xmm16, %rsi, 1, _, 0, _, 3      
   %xmm16 = VPINSRDZrm                          %xmm16, %rsi, 1, _, 0, _, 3                                
   ; CHECK: %xmm16 = VPINSRDZrr                 %xmm16, %edi, 5            
   %xmm16 = VPINSRDZrr                          %xmm16, %edi, 5                                            
body: |
   ; CHECK: %xmm16 = VCVTSI2SSZrm               %xmm16, %rdi, 1, _, 0, _
   %xmm16 = VCVTSI2SSZrm                        %xmm16, %rdi, 1, _, 0, _                                   
   ; CHECK: %xmm16 = VCVTSI2SSZrm_Int           %xmm16, %rdi, 1, _, 0, _
   %xmm16 = VCVTSI2SSZrm_Int                    %xmm16, %rdi, 1, _, 0, _                                   
   ; CHECK: %xmm16 = VCVTSI2SSZrr               %xmm16, _
   %xmm16 = VCVTSI2SSZrr                        %xmm16, _                                                  
   ; CHECK: %xmm16 = VCVTSI2SSZrr_Int           %xmm16, _
   %xmm16 = VCVTSI2SSZrr_Int                    %xmm16, _                                                  
+  ; CHECK: %xmm16 = VCVTSI642SDZrm             %xmm16, %rdi, 1, _, 0, _
+  %xmm16 = VCVTSI642SDZrm                      %xmm16, %rdi, 1, _, 0, _
+  ; CHECK: %xmm16 = VCVTSI642SDZrm_Int         %xmm16, %rdi, 1, _, 0, _
+  %xmm16 = VCVTSI642SDZrm_Int                  %xmm16, %rdi, 1, _, 0, _
+  ; CHECK: %xmm16 = VCVTSI642SDZrr             %xmm16, _
+  %xmm16 = VCVTSI642SDZrr                      %xmm16, _
+  ; CHECK: %xmm16 = VCVTSI642SDZrr_Int         %xmm16, _
+  %xmm16 = VCVTSI642SDZrr_Int                  %xmm16, _
+  ; CHECK: %xmm16 = VCVTSI642SSZrm             %xmm16, %rdi, 1, _, 0, _ 
+  %xmm16 = VCVTSI642SSZrm                      %xmm16, %rdi, 1, _, 0, _
+  ; CHECK: %xmm16 = VCVTSI642SSZrm_Int         %xmm16, %rdi, 1, _, 0, _
+  %xmm16 = VCVTSI642SSZrm_Int                  %xmm16, %rdi, 1, _, 0, _
+  ; CHECK: %xmm16 = VCVTSI642SSZrr             %xmm16, _ 
+  %xmm16 = VCVTSI642SSZrr                      %xmm16, _
+  ; CHECK: %xmm16 = VCVTSI642SSZrr_Int         %xmm16, _
+  %xmm16 = VCVTSI642SSZrr_Int                  %xmm16, _
   ; CHECK: %xmm16 = VCVTSS2SDZrm               %xmm16, %rdi, 1, _, 0, _
   %xmm16 = VCVTSS2SDZrm                        %xmm16, %rdi, 1, _, 0, _                                   
   ; CHECK: %xmm16 = VCVTSS2SDZrr               %xmm16, _
   %xmm16 = VCVTSS2SDZrr                        %xmm16, _                                                  
   ; CHECK: %rdi = VCVTSS2SI64Zrm               %rdi, %xmm16, 1, _, 0
   %rdi = VCVTSS2SI64Zrm                        %rdi, %xmm16, 1, _, 0                                      
   ; CHECK: %rdi = VCVTSS2SI64Zrr               %xmm16
   %rdi = VCVTSS2SI64Zrr                        %xmm16                                                     
body: |
   ; CHECK: %xmm16 = VMOVDI2SSZrr               %eax
   %xmm16 = VMOVDI2SSZrr                        %eax                                                       
   ; CHECK: VMOVSDZmr                           %rdi, %xmm16, _, _, _, _
   VMOVSDZmr                                    %rdi, %xmm16, _, _, _, _                                   
   ; CHECK: %xmm16 = VMOVSDZrm                  %rip, _, _, _, _
   %xmm16 = VMOVSDZrm                           %rip, _, _, _, _                                           
   ; CHECK: %xmm16 = VMOVSDZrr                  %xmm16, _
   %xmm16 = VMOVSDZrr                           %xmm16, _                                                  
+  ; CHECK: %xmm16 = VMOVSDZrr_REV              %xmm16, _
+  %xmm16 = VMOVSDZrr_REV                       %xmm16, _                                                
+  ; CHECK: %rax = VMOVSDto64Zrr                %xmm16
+  %rax = VMOVSDto64Zrr                         %xmm16
+  ; CHECK: VMOVSDto64Zmr                       %rdi, %xmm16, _, _, _, _
+  VMOVSDto64Zmr                                %rdi, %xmm16, _, _, _, _
   ; CHECK: VMOVSSZmr                           %rdi, %xmm16, _, _, _, _
   VMOVSSZmr                                    %rdi, %xmm16, _, _, _, _                                   
   ; CHECK: %xmm16 = VMOVSSZrm                  %rip, _, _, _, _
   %xmm16 = VMOVSSZrm                           %rip, _, _, _, _                                           
   ; CHECK: %xmm16 = VMOVSSZrr                  %xmm16, _
   %xmm16 = VMOVSSZrr                           %xmm16, _                                                  
   ; CHECK: %xmm16 = VMOVSSZrr_REV              %xmm16, _
   %xmm16 = VMOVSSZrr_REV                       %xmm16, _                                                  
+  ; CHECK: VMOVSS2DIZmr                        %rdi, %xmm16, _, _, _, _
+  VMOVSS2DIZmr                                 %rdi, %xmm16, _, _, _, _
+  ; CHECK: %eax = VMOVSS2DIZrr                 %xmm16
+  %eax = VMOVSS2DIZrr                          %xmm16
   ; CHECK: %xmm16 = VMOV64toPQIZrr             %rdi
   %xmm16 = VMOV64toPQIZrr                      %rdi                                                       
+  ; CHECK: %xmm16 = VMOV64toPQIZrm             %rdi, _, _, _, _
+  %xmm16 = VMOV64toPQIZrm                      %rdi, _, _, _, _
   ; CHECK: %xmm16 = VMOV64toSDZrr              %rdi 
   %xmm16 = VMOV64toSDZrr                       %rdi                                                       
   ; CHECK: %xmm16 = VMOVDI2PDIZrm              %rip, _, _, _, _
   %xmm16 = VMOVDI2PDIZrm                       %rip, _, _, _, _                                           
   ; CHECK: %xmm16 = VMOVDI2PDIZrr              %edi
   %xmm16 = VMOVDI2PDIZrr                       %edi                                                       
   ; CHECK: %xmm16 = VMOVLHPSZrr                %xmm16, _
   %xmm16 = VMOVLHPSZrr                         %xmm16, _                                                  
   ; CHECK: %xmm16 = VMOVHLPSZrr                %xmm16, _
   %xmm16 = VMOVHLPSZrr                         %xmm16, _                                                  
   ; CHECK: VMOVPDI2DIZmr                       %rdi, %xmm16, _, _, _, _
   VMOVPDI2DIZmr                                %rdi, %xmm16, _, _, _, _                                   
   ; CHECK: %edi = VMOVPDI2DIZrr                %xmm16
   %edi = VMOVPDI2DIZrr                         %xmm16                                                     
+  ; CHECK: %xmm16 = VMOVPQI2QIZrr              %xmm16
+  %xmm16 = VMOVPQI2QIZrr                       %xmm16
   ; CHECK: VMOVPQI2QIZmr                       %rdi, %xmm16, _, _, _, _
   VMOVPQI2QIZmr                                %rdi, %xmm16, _, _, _, _                                   
   ; CHECK: %rdi = VMOVPQIto64Zrr               %xmm16
   %rdi = VMOVPQIto64Zrr                        %xmm16                                                     
+  ; CHECK: VMOVPQIto64Zmr                      %rdi, %xmm16, _, _, _, _
+  VMOVPQIto64Zmr                               %rdi, %xmm16, _, _, _, _
   ; CHECK: %xmm16 = VMOVQI2PQIZrm              %rip, _, _, _, _
   %xmm16 = VMOVQI2PQIZrm                       %rip, _, _, _, _                                           
   ; CHECK: %xmm16 = VMOVZPQILo2PQIZrr          %xmm16
   %xmm16 = VMOVZPQILo2PQIZrr                   %xmm16                                                     
   ; CHECK: Int_VCOMISDZrm                      %xmm16, %rdi, _, _, _, _, implicit-def %eflags
   Int_VCOMISDZrm                               %xmm16, %rdi, _, _, _, _, implicit-def %eflags             
   ; CHECK: Int_VCOMISDZrr                      %xmm16, %xmm1, implicit-def %eflags  
   Int_VCOMISDZrr                               %xmm16, %xmm1, implicit-def %eflags                        

test/CodeGen/X86/sse-intrinsics-x86_64.ll

 ;
 ; AVX2-LABEL: test_x86_sse_cvtsi642ss:
 ; AVX2:       ## BB#0:
 ; AVX2-NEXT:    vcvtsi2ssq %rdi, %xmm0, %xmm0 ## encoding: [0xc4,0xe1,0xfa,0x2a,0xc7]
 ; AVX2-NEXT:    retq ## encoding: [0xc3]
 ;
 ; SKX-LABEL: test_x86_sse_cvtsi642ss:
 ; SKX:       ## BB#0:
-; SKX-NEXT:    vcvtsi2ssq %rdi, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0xfe,0x08,0x2a,0xc7]
+; SKX-NEXT:    vcvtsi2ssq %rdi, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe1,0xfa,0x2a,0xc7]
 ; SKX-NEXT:    retq ## encoding: [0xc3]
   %res = call <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float> %a0, i64 %a1) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
 declare <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float>, i64) nounwind readnone
 
 
 define i64 @test_x86_sse_cvttss2si64(<4 x float> %a0) {

test/CodeGen/X86/sse2-intrinsics-x86_64.ll

 ;
 ; AVX2-LABEL: test_x86_sse2_cvtsi642sd:
 ; AVX2:       ## BB#0:
 ; AVX2-NEXT:    vcvtsi2sdq %rdi, %xmm0, %xmm0 ## encoding: [0xc4,0xe1,0xfb,0x2a,0xc7]
 ; AVX2-NEXT:    retq ## encoding: [0xc3]
 ;
 ; SKX-LABEL: test_x86_sse2_cvtsi642sd:
 ; SKX:       ## BB#0:
-; SKX-NEXT:    vcvtsi2sdq %rdi, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0xff,0x08,0x2a,0xc7]
+; SKX-NEXT:    vcvtsi2sdq %rdi, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe1,0xfb,0x2a,0xc7]
 ; SKX-NEXT:    retq ## encoding: [0xc3]
   %res = call <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double> %a0, i64 %a1) ; <<2 x double>> [#uses=1]
   ret <2 x double> %res
 }
 declare <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double>, i64) nounwind readnone
 
 
 define i64 @test_x86_sse2_cvttsd2si64(<2 x double> %a0) {

test/CodeGen/X86/sse41-intrinsics-x86.ll

 ; AVX2-LABEL: test_x86_sse41_insertps:
 ; AVX2:       ## BB#0:
 ; AVX2-NEXT:    vinsertps $17, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x21,0xc1,0x11]
 ; AVX2-NEXT:    ## xmm0 = zero,xmm1[0],xmm0[2,3]
 ; AVX2-NEXT:    retl ## encoding: [0xc3]
 ;
 ; SKX-LABEL: test_x86_sse41_insertps:
 ; SKX:       ## BB#0:
-; SKX-NEXT:    vinsertps $17, %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf3,0x7d,0x08,0x21,0xc1,0x11]
+; SKX-NEXT:    vinsertps $17, %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x21,0xc1,0x11]
 ; SKX-NEXT:    ## xmm0 = zero,xmm1[0],xmm0[2,3]
 ; SKX-NEXT:    retl ## encoding: [0xc3]
   %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i8 17) ; <<4 x float>> [#uses=1]
   ret <4 x float> %res
 }
 declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i8) nounwind readnone
 
 

test/CodeGen/X86/subvector-broadcast.ll

 ; X32-AVX:       ## BB#0:
 ; X32-AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-AVX-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X32-AVX-NEXT:    retl
 ;
 ; X32-AVX512F-LABEL: test_broadcast_2f64_4f64:
 ; X32-AVX512F:       ## BB#0:
 ; X32-AVX512F-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-AVX512F-NEXT:    vbroadcastf32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X32-AVX512F-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X32-AVX512F-NEXT:    retl
 ;
 ; X32-AVX512BW-LABEL: test_broadcast_2f64_4f64:
 ; X32-AVX512BW:       ## BB#0:
 ; X32-AVX512BW-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-AVX512BW-NEXT:    vbroadcastf32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X32-AVX512BW-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X32-AVX512BW-NEXT:    retl
 ;
 ; X32-AVX512DQ-LABEL: test_broadcast_2f64_4f64:
 ; X32-AVX512DQ:       ## BB#0:
 ; X32-AVX512DQ-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-AVX512DQ-NEXT:    vbroadcastf64x2 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X32-AVX512DQ-NEXT:    retl
 ;
 ; X64-AVX-LABEL: test_broadcast_2f64_4f64:
 ; X64-AVX:       ## BB#0:
 ; X64-AVX-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX-NEXT:    retq
 ;
 ; X64-AVX512F-LABEL: test_broadcast_2f64_4f64:
 ; X64-AVX512F:       ## BB#0:
-; X64-AVX512F-NEXT:    vbroadcastf32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X64-AVX512F-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX512F-NEXT:    retq
 ;
 ; X64-AVX512BW-LABEL: test_broadcast_2f64_4f64:
 ; X64-AVX512BW:       ## BB#0:
-; X64-AVX512BW-NEXT:    vbroadcastf32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X64-AVX512BW-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX512BW-NEXT:    retq
 ;
 ; X64-AVX512DQ-LABEL: test_broadcast_2f64_4f64:
 ; X64-AVX512DQ:       ## BB#0:
 ; X64-AVX512DQ-NEXT:    vbroadcastf64x2 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX512DQ-NEXT:    retq
  %1 = load <2 x double>, <2 x double> *%p
  %2 = shufflevector <2 x double> %1, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>

 ; X32-AVX:       ## BB#0:
 ; X32-AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-AVX-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X32-AVX-NEXT:    retl
 ;
 ; X32-AVX512F-LABEL: test_broadcast_2i64_4i64:
 ; X32-AVX512F:       ## BB#0:
 ; X32-AVX512F-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-AVX512F-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X32-AVX512F-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X32-AVX512F-NEXT:    retl
 ;
 ; X32-AVX512BW-LABEL: test_broadcast_2i64_4i64:
 ; X32-AVX512BW:       ## BB#0:
 ; X32-AVX512BW-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-AVX512BW-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X32-AVX512BW-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X32-AVX512BW-NEXT:    retl
 ;
 ; X32-AVX512DQ-LABEL: test_broadcast_2i64_4i64:
 ; X32-AVX512DQ:       ## BB#0:
 ; X32-AVX512DQ-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-AVX512DQ-NEXT:    vbroadcasti64x2 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X32-AVX512DQ-NEXT:    retl
 ;
 ; X64-AVX-LABEL: test_broadcast_2i64_4i64:
 ; X64-AVX:       ## BB#0:
 ; X64-AVX-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX-NEXT:    retq
 ;
 ; X64-AVX512F-LABEL: test_broadcast_2i64_4i64:
 ; X64-AVX512F:       ## BB#0:
-; X64-AVX512F-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X64-AVX512F-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX512F-NEXT:    retq
 ;
 ; X64-AVX512BW-LABEL: test_broadcast_2i64_4i64:
 ; X64-AVX512BW:       ## BB#0:
-; X64-AVX512BW-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X64-AVX512BW-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX512BW-NEXT:    retq
 ;
 ; X64-AVX512DQ-LABEL: test_broadcast_2i64_4i64:
 ; X64-AVX512DQ:       ## BB#0:
 ; X64-AVX512DQ-NEXT:    vbroadcasti64x2 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX512DQ-NEXT:    retq
  %1 = load <2 x i64>, <2 x i64> *%p
  %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>

 ; X64-AVX512-NEXT:    vbroadcasti64x4 {{.*#+}} zmm0 = mem[0,1,2,3,0,1,2,3]
 ; X64-AVX512-NEXT:    retq
  %1 = load <4 x i64>, <4 x i64> *%p
  %2 = shufflevector <4 x i64> %1, <4 x i64> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
  ret <8 x i64> %2
 }
 
 define <8 x float> @test_broadcast_4f32_8f32(<4 x float> *%p) nounwind {
-; X32-AVX-LABEL: test_broadcast_4f32_8f32:
-; X32-AVX:       ## BB#0:
-; X32-AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-AVX-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X32-AVX-NEXT:    retl
-;
-; X32-AVX512-LABEL: test_broadcast_4f32_8f32:
-; X32-AVX512:       ## BB#0:
-; X32-AVX512-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-AVX512-NEXT:    vbroadcastf32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
-; X32-AVX512-NEXT:    retl
-;
-; X64-AVX-LABEL: test_broadcast_4f32_8f32:
-; X64-AVX:       ## BB#0:
-; X64-AVX-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X64-AVX-NEXT:    retq
+; X32-LABEL: test_broadcast_4f32_8f32:
+; X32:       ## BB#0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
+; X32-NEXT:    retl
 ;
-; X64-AVX512-LABEL: test_broadcast_4f32_8f32:
-; X64-AVX512:       ## BB#0:
-; X64-AVX512-NEXT:    vbroadcastf32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
-; X64-AVX512-NEXT:    retq
+; X64-LABEL: test_broadcast_4f32_8f32:
+; X64:       ## BB#0:
+; X64-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
+; X64-NEXT:    retq
  %1 = load <4 x float>, <4 x float> *%p
  %2 = shufflevector <4 x float> %1, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
  ret <8 x float> %2
 }
 
 define <16 x float> @test_broadcast_4f32_16f32(<4 x float> *%p) nounwind {
 ; X32-AVX-LABEL: test_broadcast_4f32_16f32:
 ; X32-AVX:       ## BB#0:

 ; X32-AVX:       ## BB#0:
 ; X32-AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-AVX-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X32-AVX-NEXT:    retl
 ;
 ; X32-AVX512-LABEL: test_broadcast_4i32_8i32:
 ; X32-AVX512:       ## BB#0:
 ; X32-AVX512-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-AVX512-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X32-AVX512-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X32-AVX512-NEXT:    retl
 ;
 ; X64-AVX-LABEL: test_broadcast_4i32_8i32:
 ; X64-AVX:       ## BB#0:
 ; X64-AVX-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX-NEXT:    retq
 ;
 ; X64-AVX512-LABEL: test_broadcast_4i32_8i32:
 ; X64-AVX512:       ## BB#0:
-; X64-AVX512-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X64-AVX512-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX512-NEXT:    retq
  %1 = load <4 x i32>, <4 x i32> *%p
  %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
  ret <8 x i32> %2
 }
 
 define <16 x i32> @test_broadcast_4i32_16i32(<4 x i32> *%p) nounwind {
 ; X32-AVX1-LABEL: test_broadcast_4i32_16i32:

 ; X32-AVX:       ## BB#0:
 ; X32-AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-AVX-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X32-AVX-NEXT:    retl
 ;
 ; X32-AVX512-LABEL: test_broadcast_8i16_16i16:
 ; X32-AVX512:       ## BB#0:
 ; X32-AVX512-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-AVX512-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X32-AVX512-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X32-AVX512-NEXT:    retl
 ;
 ; X64-AVX-LABEL: test_broadcast_8i16_16i16:
 ; X64-AVX:       ## BB#0:
 ; X64-AVX-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX-NEXT:    retq
 ;
 ; X64-AVX512-LABEL: test_broadcast_8i16_16i16:
 ; X64-AVX512:       ## BB#0:
-; X64-AVX512-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X64-AVX512-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX512-NEXT:    retq
  %1 = load <8 x i16>, <8 x i16> *%p
  %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  ret <16 x i16> %2
 }
 
 define <32 x i16> @test_broadcast_8i16_32i16(<8 x i16> *%p) nounwind {
 ; X32-AVX1-LABEL: test_broadcast_8i16_32i16:
 ; X32-AVX1:       ## BB#0:
 ; X32-AVX1-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-AVX1-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X32-AVX1-NEXT:    vmovdqa %ymm0, %ymm1
 ; X32-AVX1-NEXT:    retl
 ;
 ; X32-AVX2-LABEL: test_broadcast_8i16_32i16:
 ; X32-AVX2:       ## BB#0:
 ; X32-AVX2-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-AVX2-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X32-AVX2-NEXT:    vmovaps %ymm0, %ymm1
 ; X32-AVX2-NEXT:    retl
 ;
 ; X32-AVX512F-LABEL: test_broadcast_8i16_32i16:
 ; X32-AVX512F:       ## BB#0:
 ; X32-AVX512F-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-AVX512F-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X32-AVX512F-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X32-AVX512F-NEXT:    vmovdqa %ymm0, %ymm1
 ; X32-AVX512F-NEXT:    retl
 ;
 ; X32-AVX512BW-LABEL: test_broadcast_8i16_32i16:
 ; X32-AVX512BW:       ## BB#0:
 ; X32-AVX512BW-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-AVX512BW-NEXT:    vbroadcasti32x4 {{.*#+}} zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
 ; X32-AVX512BW-NEXT:    retl
 ;
 ; X32-AVX512DQ-LABEL: test_broadcast_8i16_32i16:
 ; X32-AVX512DQ:       ## BB#0:
 ; X32-AVX512DQ-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-AVX512DQ-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X32-AVX512DQ-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X32-AVX512DQ-NEXT:    vmovdqa %ymm0, %ymm1
 ; X32-AVX512DQ-NEXT:    retl
 ;
 ; X64-AVX1-LABEL: test_broadcast_8i16_32i16:
 ; X64-AVX1:       ## BB#0:
 ; X64-AVX1-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX1-NEXT:    vmovdqa %ymm0, %ymm1
 ; X64-AVX1-NEXT:    retq
 ;
 ; X64-AVX2-LABEL: test_broadcast_8i16_32i16:
 ; X64-AVX2:       ## BB#0:
 ; X64-AVX2-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX2-NEXT:    vmovaps %ymm0, %ymm1
 ; X64-AVX2-NEXT:    retq
 ;
 ; X64-AVX512F-LABEL: test_broadcast_8i16_32i16:
 ; X64-AVX512F:       ## BB#0:
-; X64-AVX512F-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X64-AVX512F-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX512F-NEXT:    vmovdqa %ymm0, %ymm1
 ; X64-AVX512F-NEXT:    retq
 ;
 ; X64-AVX512BW-LABEL: test_broadcast_8i16_32i16:
 ; X64-AVX512BW:       ## BB#0:
 ; X64-AVX512BW-NEXT:    vbroadcasti32x4 {{.*#+}} zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
 ; X64-AVX512BW-NEXT:    retq
 ;
 ; X64-AVX512DQ-LABEL: test_broadcast_8i16_32i16:
 ; X64-AVX512DQ:       ## BB#0:
-; X64-AVX512DQ-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X64-AVX512DQ-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX512DQ-NEXT:    vmovdqa %ymm0, %ymm1
 ; X64-AVX512DQ-NEXT:    retq
  %1 = load <8 x i16>, <8 x i16> *%p
  %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  ret <32 x i16> %2
 }
 
 define <32 x i16> @test_broadcast_16i16_32i16(<16 x i16> *%p) nounwind {

 ; X32-AVX:       ## BB#0:
 ; X32-AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-AVX-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X32-AVX-NEXT:    retl
 ;
 ; X32-AVX512-LABEL: test_broadcast_16i8_32i8:
 ; X32-AVX512:       ## BB#0:
 ; X32-AVX512-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-AVX512-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X32-AVX512-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X32-AVX512-NEXT:    retl
 ;
 ; X64-AVX-LABEL: test_broadcast_16i8_32i8:
 ; X64-AVX:       ## BB#0:
 ; X64-AVX-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX-NEXT:    retq
 ;
 ; X64-AVX512-LABEL: test_broadcast_16i8_32i8:
 ; X64-AVX512:       ## BB#0:
-; X64-AVX512-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X64-AVX512-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX512-NEXT:    retq
  %1 = load <16 x i8>, <16 x i8> *%p
  %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  ret <32 x i8> %2
 }
 
 define <64 x i8> @test_broadcast_16i8_64i8(<16 x i8> *%p) nounwind {
 ; X32-AVX1-LABEL: test_broadcast_16i8_64i8:
 ; X32-AVX1:       ## BB#0:
 ; X32-AVX1-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-AVX1-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X32-AVX1-NEXT:    vmovdqa %ymm0, %ymm1
 ; X32-AVX1-NEXT:    retl
 ;
 ; X32-AVX2-LABEL: test_broadcast_16i8_64i8:
 ; X32-AVX2:       ## BB#0:
 ; X32-AVX2-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-AVX2-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X32-AVX2-NEXT:    vmovaps %ymm0, %ymm1
 ; X32-AVX2-NEXT:    retl
 ;
 ; X32-AVX512F-LABEL: test_broadcast_16i8_64i8:
 ; X32-AVX512F:       ## BB#0:
 ; X32-AVX512F-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-AVX512F-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X32-AVX512F-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X32-AVX512F-NEXT:    vmovdqa %ymm0, %ymm1
 ; X32-AVX512F-NEXT:    retl
 ;
 ; X32-AVX512BW-LABEL: test_broadcast_16i8_64i8:
 ; X32-AVX512BW:       ## BB#0:
 ; X32-AVX512BW-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-AVX512BW-NEXT:    vbroadcasti32x4 {{.*#+}} zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
 ; X32-AVX512BW-NEXT:    retl
 ;
 ; X32-AVX512DQ-LABEL: test_broadcast_16i8_64i8:
 ; X32-AVX512DQ:       ## BB#0:
 ; X32-AVX512DQ-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-AVX512DQ-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X32-AVX512DQ-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X32-AVX512DQ-NEXT:    vmovdqa %ymm0, %ymm1
 ; X32-AVX512DQ-NEXT:    retl
 ;
 ; X64-AVX1-LABEL: test_broadcast_16i8_64i8:
 ; X64-AVX1:       ## BB#0:
 ; X64-AVX1-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX1-NEXT:    vmovdqa %ymm0, %ymm1
 ; X64-AVX1-NEXT:    retq
 ;
 ; X64-AVX2-LABEL: test_broadcast_16i8_64i8:
 ; X64-AVX2:       ## BB#0:
 ; X64-AVX2-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX2-NEXT:    vmovaps %ymm0, %ymm1
 ; X64-AVX2-NEXT:    retq
 ;
 ; X64-AVX512F-LABEL: test_broadcast_16i8_64i8:
 ; X64-AVX512F:       ## BB#0:
-; X64-AVX512F-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X64-AVX512F-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX512F-NEXT:    vmovdqa %ymm0, %ymm1
 ; X64-AVX512F-NEXT:    retq
 ;
 ; X64-AVX512BW-LABEL: test_broadcast_16i8_64i8:
 ; X64-AVX512BW:       ## BB#0:
 ; X64-AVX512BW-NEXT:    vbroadcasti32x4 {{.*#+}} zmm0 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
 ; X64-AVX512BW-NEXT:    retq
 ;
 ; X64-AVX512DQ-LABEL: test_broadcast_16i8_64i8:
 ; X64-AVX512DQ:       ## BB#0:
-; X64-AVX512DQ-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; X64-AVX512DQ-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; X64-AVX512DQ-NEXT:    vmovdqa %ymm0, %ymm1
 ; X64-AVX512DQ-NEXT:    retq
  %1 = load <16 x i8>, <16 x i8> *%p
  %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  ret <64 x i8> %2
 }
 
 define <64 x i8> @test_broadcast_32i8_64i8(<32 x i8> *%p) nounwind {

test/CodeGen/X86/vector-shuffle-256-v4.ll

 ;
 ; AVX2-LABEL: splat128_mem_v4i64_from_v2i64:
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; AVX2-NEXT:    retq
 ;
 ; AVX512VL-LABEL: splat128_mem_v4i64_from_v2i64:
 ; AVX512VL:       # BB#0:
-; AVX512VL-NEXT:    vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
+; AVX512VL-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
 ; AVX512VL-NEXT:    retq
   %v = load <2 x i64>, <2 x i64>* %ptr
   %shuffle = shufflevector <2 x i64> %v, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
   ret <4 x i64> %shuffle
 }
 
 define <4 x double> @splat128_mem_v4f64_from_v2f64(<2 x double>* %ptr) {
-; AVX1-LABEL: splat128_mem_v4f64_from_v2f64:
-; AVX1:       # BB#0:
-; AVX1-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; AVX1-NEXT:    retq
-;
-; AVX2-LABEL: splat128_mem_v4f64_from_v2f64:
-; AVX2:       # BB#0:
-; AVX2-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; AVX2-NEXT:    retq
-;
-; AVX512VL-LABEL: splat128_mem_v4f64_from_v2f64:
-; AVX512VL:       # BB#0:
-; AVX512VL-NEXT:    vbroadcastf32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
-; AVX512VL-NEXT:    retq
+; ALL-LABEL: splat128_mem_v4f64_from_v2f64:
+; ALL:       # BB#0:
+; ALL-NEXT:    vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
+; ALL-NEXT:    retq
   %v = load <2 x double>, <2 x double>* %ptr
   %shuffle = shufflevector <2 x double> %v, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
   ret <4 x double> %shuffle
 }
 
 define <4 x double> @broadcast_v4f64_0000_from_v2i64(<2 x i64> %a0) {
 ; AVX1-LABEL: broadcast_v4f64_0000_from_v2i64:
 ; AVX1:       # BB#0:

test/CodeGen/X86/vselect-pcmp.ll

; AVX512-NEXT:    retq
   %tr = icmp slt <16 x i8> %mask, zeroinitializer
   %z = select <16 x i1> %tr, <16 x i8> %x, <16 x i8> %y
   ret <16 x i8> %z
 }
 
 ; Sorry 16-bit, you're not important enough to support?
 
 define <8 x i16> @signbit_sel_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %mask) {
-; AVX12F-LABEL: signbit_sel_v8i16:
-; AVX12F:       # BB#0:
-; AVX12F-NEXT:    vpxor %xmm3, %xmm3, %xmm3
-; AVX12F-NEXT:    vpcmpgtw %xmm2, %xmm3, %xmm2
-; AVX12F-NEXT:    vpandn %xmm1, %xmm2, %xmm1
-; AVX12F-NEXT:    vpand %xmm2, %xmm0, %xmm0
-; AVX12F-NEXT:    vpor %xmm1, %xmm0, %xmm0
-; AVX12F-NEXT:    retq
-;
-; AVX512VL-LABEL: signbit_sel_v8i16:
-; AVX512VL:       # BB#0:
-; AVX512VL-NEXT:    vpxor %xmm3, %xmm3, %xmm3
-; AVX512VL-NEXT:    vpcmpgtw %xmm2, %xmm3, %xmm2
-; AVX512VL-NEXT:    vpandnq %xmm1, %xmm2, %xmm1
-; AVX512VL-NEXT:    vpand %xmm2, %xmm0, %xmm0
-; AVX512VL-NEXT:    vpor %xmm1, %xmm0, %xmm0
-; AVX512VL-NEXT:    retq
+; AVX-LABEL: signbit_sel_v8i16:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpxor %xmm3, %xmm3, %xmm3
+; AVX-NEXT:    vpcmpgtw %xmm2, %xmm3, %xmm2
+; AVX-NEXT:    vpandn %xmm1, %xmm2, %xmm1
+; AVX-NEXT:    vpand %xmm2, %xmm0, %xmm0
+; AVX-NEXT:    vpor %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    retq
   %tr = icmp slt <8 x i16> %mask, zeroinitializer
   %z = select <8 x i1> %tr, <8 x i16> %x, <8 x i16> %y
   ret <8 x i16> %z
 }
 
 define <4 x i32> @signbit_sel_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
 ; AVX12F-LABEL: signbit_sel_v4i32:
 ; AVX12F:       # BB#0:

 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vpxor %ymm3, %ymm3, %ymm3
 ; AVX2-NEXT:    vpcmpgtw %ymm2, %ymm3, %ymm2
 ; AVX2-NEXT:    vpandn %ymm1, %ymm2, %ymm1
 ; AVX2-NEXT:    vpand %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpor %ymm1, %ymm0, %ymm0
 ; AVX2-NEXT:    retq
 ;
-; AVX512F-LABEL: signbit_sel_v16i16:
-; AVX512F:       # BB#0:
-; AVX512F-NEXT:    vpxor %ymm3, %ymm3, %ymm3
-; AVX512F-NEXT:    vpcmpgtw %ymm2, %ymm3, %ymm2
-; AVX512F-NEXT:    vpandn %ymm1, %ymm2, %ymm1
-; AVX512F-NEXT:    vpand %ymm2, %ymm0, %ymm0
-; AVX512F-NEXT:    vpor %ymm1, %ymm0, %ymm0
-; AVX512F-NEXT:    retq
-;
-; AVX512VL-LABEL: signbit_sel_v16i16:
-; AVX512VL:       # BB#0:
-; AVX512VL-NEXT:    vpxor %ymm3, %ymm3, %ymm3
-; AVX512VL-NEXT:    vpcmpgtw %ymm2, %ymm3, %ymm2
-; AVX512VL-NEXT:    vpandnq %ymm1, %ymm2, %ymm1
-; AVX512VL-NEXT:    vpand %ymm2, %ymm0, %ymm0
-; AVX512VL-NEXT:    vpor %ymm1, %ymm0, %ymm0
-; AVX512VL-NEXT:    retq
+; AVX512-LABEL: signbit_sel_v16i16:
+; AVX512:       # BB#0:
+; AVX512-NEXT:    vpxor %ymm3, %ymm3, %ymm3
+; AVX512-NEXT:    vpcmpgtw %ymm2, %ymm3, %ymm2
+; AVX512-NEXT:    vpandn %ymm1, %ymm2, %ymm1
+; AVX512-NEXT:    vpand %ymm2, %ymm0, %ymm0
+; AVX512-NEXT:    vpor %ymm1, %ymm0, %ymm0
+; AVX512-NEXT:    retq
   %tr = icmp slt <16 x i16> %mask, zeroinitializer
   %z = select <16 x i1> %tr, <16 x i16> %x, <16 x i16> %y
   ret <16 x i16> %z
 }
 
 define <8 x i32> @signbit_sel_v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i32> %mask) {
 ; AVX12-LABEL: signbit_sel_v8i32:
 ; AVX12:       # BB#0: