Update TrapCode based on Trap Handler ABI.

[wdng]

Summary

Update TrapCode based on Trap Handler ABI:

HSA debugtrap (arg)	s_trap 0x01	SGPR0-1: queue_ptr VGPR0: arg	Reserved for HSA debugtrap intrinsic (not implemented).
llvm.trap	s_trap 0x02	SGPR0-1: queue_ptr	Causes dispatch to be terminated and its associated queue put into the error state.
llvm.debugtrap	s_trap 0x03	SGPR0-1: queue_ptr	If debugger not installed handled same as llvm.trap.

[tony-tye]

lib/Target/AMDGPU/AMDGPUSubtarget.h

76–86

Suggest renaming to TrapID which match hardware terminology. Would need updating in other places.

To match the trap handler doc this should be:

enum TrapID {
    TrapIDHardwareReserved = 0,
    TrapIDHSADebugTrap = 1,
    TrapIDLLVMTrap = 2,
    TrapIDLLVMDebugTrap = 3,
    TrapIDDebugBreakpoint = 7,
    TrapIDDebugReserved8 = 8,
    TrapIDDebugReservedFE = 0xfe,
    TrapIDDebugReservedFF = 0xff
  };

lib/Target/AMDGPU/SIInstrInfo.td

633–634

Suggest rename to TRAPID to match hardware terminology.

[wdng]

Address code reviews.

[kzhuravl]

lib/Target/AMDGPU/AMDGPUSubtarget.h

76–86

You should also rename remaining TrapCode* to TrapID*.

[kzhuravl]

lib/Target/AMDGPU/AMDGPUSubtarget.h

76–77

This should be *TrapIDHardwareReserved*.

[wdng]

Address code reviews, sorry I missed name changes inside the enum block.

[tony-tye]

LGTM

lib/Target/AMDGPU/AMDGPUSubtarget.h

88–90

Given that the HSADEBUGTRAP is no longer being used, is this enumeration being used now? If not it should be deleted.

lib/Target/AMDGPU/AMDGPUSubtarget.h

enum {
     ISAVersion9_0_0,
     ISAVersion9_0_1
   };
 
   enum TrapHandlerAbi {
     TrapHandlerAbiNone = 0,
     TrapHandlerAbiHsa = 1
   };
 
-  enum TrapCode {
-    TrapCodeBreakPoint = 0,
-    TrapCodeLLVMTrap = 1,
-    TrapCodeLLVMDebugTrap = 2,
-    TrapCodeHSADebugTrap = 3
+  enum TrapID {
+    TrapIDHardwareReserved = 0,
+    TrapIDHSADebugTrap = 1,
+    TrapIDLLVMTrap = 2,
+    TrapIDLLVMDebugTrap = 3,
+    TrapIDDebugBreakpoint = 7,
+    TrapIDDebugReserved8 = 8,
+    TrapIDDebugReservedFE = 0xfe,
+    TrapIDDebugReservedFF = 0xff
   };
 
   enum TrapRegValues {
-    TrapCodeLLVMTrapRegValue = 1
+    LLVMTrapHandlerRegValue = 1
   };
 
 protected:
   // Basic subtarget description.
   Triple TargetTriple;
   Generation Gen;
   unsigned IsaVersion;
   unsigned WavefrontSize;
   int LocalMemorySize;

lib/Target/AMDGPU/SIISelLowering.cpp

if (Subtarget->getTrapHandlerAbi() == SISubtarget::TrapHandlerAbiHsa &&
 
       BuildMI(*BB, MI, DL, TII->get(AMDGPU::COPY), AMDGPU::SGPR0_SGPR1)
         .addReg(UserSGPR);
       BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_TRAP))
         .addImm(TrapType)
         .addReg(AMDGPU::SGPR0_SGPR1, RegState::Implicit);
     } else {
       switch (TrapType) {
-      case SISubtarget::TrapCodeLLVMTrap:
+      case SISubtarget::TrapIDLLVMTrap:
         BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_ENDPGM));
         break;
       case SISubtarget::TrapCodeLLVMDebugTrap: {
         DiagnosticInfoUnsupported NoTrap(*MF->getFunction(),
                                          "debugtrap handler not supported",
                                          DL,
                                          DS_Warning);
         LLVMContext &C = MF->getFunction()->getContext();

lib/Target/AMDGPU/SIInstrInfo.td

 
 def DSTCLAMP {
   int NONE = 0;
 }
 
 def DSTOMOD {
   int NONE = 0;
 }
 
-def TRAPTYPE {
-  int LLVM_TRAP = 1;
-  int LLVM_DEBUG_TRAP = 2;
+def TRAPID{
+  int LLVM_TRAP = 2;
+  int LLVM_DEBUG_TRAP = 3;
 }
 
 //===----------------------------------------------------------------------===//
 //
 // SI Instruction multiclass helpers.
 //
 // Instructions with _32 take 32-bit operands.
 // Instructions with _64 take 64-bit operands.

lib/Target/AMDGPU/SIInstructions.td

def SI_PC_ADD_REL_OFFSET : SPseudoInstSI <
   let Defs = [SCC];
 }
 
 } // End SubtargetPredicate = isGCN
 
 let Predicates = [isGCN] in {
 def : Pat<
   (trap),
-  (S_TRAP_PSEUDO TRAPTYPE.LLVM_TRAP)
+  (S_TRAP_PSEUDO TRAPID.LLVM_TRAP)
 >;
 
 def : Pat<
   (debugtrap),
-  (S_TRAP_PSEUDO TRAPTYPE.LLVM_DEBUG_TRAP)
+  (S_TRAP_PSEUDO TRAPID.LLVM_DEBUG_TRAP)
 >;
 
 def : Pat<
   (int_amdgcn_else i64:$src, bb:$target),
   (SI_ELSE $src, $target, 0)
 >;
 
 def : Pat <

test/CodeGen/AMDGPU/trap.ll

 
 ; NOMESA-TRAP: .section .AMDGPU.config
 ; NOMESA-TRAP:  .long   47180
 ; NOMESA-TRAP-NEXT: .long   144
 
 ; GCN-LABEL: {{^}}hsa_trap:
 ; HSA-TRAP: enable_trap_handler = 1
 ; HSA-TRAP: s_mov_b64 s[0:1], s[4:5]
-; HSA-TRAP: s_trap 1
+; HSA-TRAP: s_trap 2
 
 ; for llvm.trap in hsa path without ABI, direct generate s_endpgm instruction without any warning information
 ; NO-HSA-TRAP: enable_trap_handler = 0
 ; NO-HSA-TRAP: s_endpgm
 ; NO-HSA-TRAP: COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
 
 ; TRAP-BIT: enable_trap_handler = 1
 ; NO-TRAP-BIT: enable_trap_handler = 0

 ; NOMESA-TRAP: .section .AMDGPU.config
 ; NOMESA-TRAP:  .long   47180
 ; NOMESA-TRAP-NEXT: .long   144
 
 ; GCN-WARNING: warning: <unknown>:0:0: in function hsa_debugtrap void (): debugtrap handler not supported
 ; GCN-LABEL: {{^}}hsa_debugtrap:
 ; HSA-TRAP: enable_trap_handler = 1
 ; HSA-TRAP: s_mov_b64 s[0:1], s[4:5]
-; HSA-TRAP: s_trap 2
+; HSA-TRAP: s_trap 3
 
 ; for llvm.debugtrap in non-hsa path without ABI, generate a warning and a s_endpgm instruction
 ; NO-HSA-TRAP: enable_trap_handler = 0
 ; NO-HSA-TRAP: s_endpgm
 
 ; TRAP-BIT: enable_trap_handler = 1
 ; NO-TRAP-BIT: enable_trap_handler = 0
 ; NO-MESA-TRAP: s_endpgm