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[X86][AVX512] Change VCVTSS2SD and VCVTSD2SS node types to keep consistency between VEX/EVEX versions.
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Authored by aymanmus on Feb 15 2017, 7:14 AM.

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aymanmus created this revision.Feb 15 2017, 7:14 AM
craig.topper edited edge metadata.Feb 16 2017, 9:45 PM

Any idea why the tests changed?

lib/Target/X86/X86InstrAVX512.td
6108

Should we have a VCVTSD2SSZrr_Int instruction like SSE/AVX?

RKSimon added inline comments.Feb 20 2017, 8:06 AM
test/CodeGen/X86/vector-half-conversions.ll
6

Please can you add -verify-machineinstrs to these to check that the the regclass changes are still being respected.

aymanmus updated this revision to Diff 89193.Feb 21 2017, 5:08 AM

Add _Int versions for AVX512

@craig.topper I don't know exactly why the test changed.
But the diff is only with register names and slightly change in the instructions' order.

aymanmus updated this revision to Diff 89197.Feb 21 2017, 6:38 AM

Please add the new _Int instructions to X86InstrInfo::hasUndefRegUpdate() and the load folding tables.

lib/Target/X86/X86InstrAVX512.td
6053

We probably don't need a non-intrinsic rounding mode instruction. Other than the intrinsic there's no way to create a node with the rounding mode

6065

We probably don't need a non-intrinsic rounding mode instruction. Other than the intrinsic there's no way to create a node with the rounding mode

6111–6113

Can this use VCVTSD2SSZrr_Int? Is there an equivalent pattern for AVX/SSE? What does it use?

6120–6122

Can this use VCVTSS2SDZrr_Int? Is there an equivalent pattern for AVX/SSE? What does it use?

aymanmus updated this revision to Diff 89340.Feb 22 2017, 2:05 AM

Fix comments

This revision is now accepted and ready to land.Feb 22 2017, 10:56 PM
This revision was automatically updated to reflect the committed changes.