AMDGPU: Add ds_nop to assembler

[arsenm]

Forgot to commit test

[tstellar]

LGTM.

[arsenm]

r296513

lib/Target/AMDGPU/DSInstructions.td

class DS_1A_GDS <string opName> : DS_Pseudo<opName,
   let has_offset  = 0;
   let has_offset0 = 0;
   let has_offset1 = 0;
 
   let has_gds     = 0;
   let gdsValue    = 1;
 }
 
+class DS_VOID <string opName> : DS_Pseudo<opName,
+  (outs), (ins), ""> {
+  let mayLoad = 0;
+  let mayStore = 0;
+  let hasSideEffects = 1;
+  let UseNamedOperandTable = 0;
+  let AsmMatchConverter = "";
+
+  let has_vdst = 0;
+  let has_addr = 0;
+  let has_data0 = 0;
+  let has_data1 = 0;
+  let has_offset = 0;
+  let has_offset0 = 0;
+  let has_offset1 = 0;
+  let has_gds = 0;
+}
+
 class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag>
 : DS_Pseudo<opName,
   (outs VGPR_32:$vdst),
   (ins VGPR_32:$addr, VGPR_32:$data0, offset:$offset),
   "$vdst, $addr, $data0$offset",
   [(set i32:$vdst,
    (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > {
 

 def DS_APPEND        : DS_0A_RET<"ds_append">;
 def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
 }
 
 //===----------------------------------------------------------------------===//
 // Instruction definitions for CI and newer.
 //===----------------------------------------------------------------------===//
 // Remaining instructions:
-// DS_NOP
 // DS_GWS_SEMA_RELEASE_ALL
 // DS_WRAP_RTN_B32
 // DS_CNDXCHG32_RTN_B64
 // DS_CONDXCHG32_RTN_B128
 
 let SubtargetPredicate = isCIVI in {
 
 def DS_WRAP_RTN_F32 : DS_1A1D_RET <"ds_wrap_rtn_f32">,
                       AtomicNoRet<"ds_wrap_f32", 1>;
 
 let mayStore = 0 in {
 def DS_READ_B96 : DS_1A_RET<"ds_read_b96", VReg_96>;
 def DS_READ_B128: DS_1A_RET<"ds_read_b128", VReg_128>;
 } // End mayStore = 0
 
 let mayLoad = 0 in {
 def DS_WRITE_B96 : DS_1A1D_NORET<"ds_write_b96", VReg_96>;
 def DS_WRITE_B128 : DS_1A1D_NORET<"ds_write_b128", VReg_128>;
 } // End mayLoad = 0
 
+def DS_NOP : DS_VOID<"ds_nop">;
 
 } // let SubtargetPredicate = isCIVI
 
 //===----------------------------------------------------------------------===//
 // Instruction definitions for VI and newer.
 //===----------------------------------------------------------------------===//
 
 let SubtargetPredicate = isVI in {

 def DS_MSKOR_B32_si       : DS_Real_si<0xc,  DS_MSKOR_B32>;
 def DS_WRITE_B32_si       : DS_Real_si<0xd,  DS_WRITE_B32>;
 def DS_WRITE2_B32_si      : DS_Real_si<0xe,  DS_WRITE2_B32>;
 def DS_WRITE2ST64_B32_si  : DS_Real_si<0xf,  DS_WRITE2ST64_B32>;
 def DS_CMPST_B32_si       : DS_Real_si<0x10, DS_CMPST_B32>;
 def DS_CMPST_F32_si       : DS_Real_si<0x11, DS_CMPST_F32>;
 def DS_MIN_F32_si         : DS_Real_si<0x12, DS_MIN_F32>;
 def DS_MAX_F32_si         : DS_Real_si<0x13, DS_MAX_F32>;
+def DS_NOP_si             : DS_Real_si<0x14, DS_NOP>;
 def DS_GWS_INIT_si        : DS_Real_si<0x19, DS_GWS_INIT>;
 def DS_GWS_SEMA_V_si      : DS_Real_si<0x1a, DS_GWS_SEMA_V>;
 def DS_GWS_SEMA_BR_si     : DS_Real_si<0x1b, DS_GWS_SEMA_BR>;
 def DS_GWS_SEMA_P_si      : DS_Real_si<0x1c, DS_GWS_SEMA_P>;
 def DS_GWS_BARRIER_si     : DS_Real_si<0x1d, DS_GWS_BARRIER>;
 def DS_WRITE_B8_si        : DS_Real_si<0x1e, DS_WRITE_B8>;
 def DS_WRITE_B16_si       : DS_Real_si<0x1f, DS_WRITE_B16>;
 def DS_ADD_RTN_U32_si     : DS_Real_si<0x20, DS_ADD_RTN_U32>;

 def DS_MSKOR_B32_vi       : DS_Real_vi<0xc,  DS_MSKOR_B32>;
 def DS_WRITE_B32_vi       : DS_Real_vi<0xd,  DS_WRITE_B32>;
 def DS_WRITE2_B32_vi      : DS_Real_vi<0xe,  DS_WRITE2_B32>;
 def DS_WRITE2ST64_B32_vi  : DS_Real_vi<0xf,  DS_WRITE2ST64_B32>;
 def DS_CMPST_B32_vi       : DS_Real_vi<0x10, DS_CMPST_B32>;
 def DS_CMPST_F32_vi       : DS_Real_vi<0x11, DS_CMPST_F32>;
 def DS_MIN_F32_vi         : DS_Real_vi<0x12, DS_MIN_F32>;
 def DS_MAX_F32_vi         : DS_Real_vi<0x13, DS_MAX_F32>;
+def DS_NOP_vi             : DS_Real_vi<0x14, DS_NOP>;
 def DS_ADD_F32_vi         : DS_Real_vi<0x15, DS_ADD_F32>;
 def DS_GWS_INIT_vi        : DS_Real_vi<0x19, DS_GWS_INIT>;
 def DS_GWS_SEMA_V_vi      : DS_Real_vi<0x1a, DS_GWS_SEMA_V>;
 def DS_GWS_SEMA_BR_vi     : DS_Real_vi<0x1b, DS_GWS_SEMA_BR>;
 def DS_GWS_SEMA_P_vi      : DS_Real_vi<0x1c, DS_GWS_SEMA_P>;
 def DS_GWS_BARRIER_vi     : DS_Real_vi<0x1d, DS_GWS_BARRIER>;
 def DS_WRITE_B8_vi        : DS_Real_vi<0x1e, DS_WRITE_B8>;
 def DS_WRITE_B16_vi       : DS_Real_vi<0x1f, DS_WRITE_B16>;

test/MC/AMDGPU/ds.s

 // NOSI: error: instruction not supported on this GPU
 // CI:   ds_read_b128 v[8:11], v2 ; encoding: [0x00,0x00,0xfc,0xdb,0x02,0x00,0x00,0x08]
 // VI:   ds_read_b128 v[8:11], v2 ; encoding: [0x00,0x00,0xfe,0xd9,0x02,0x00,0x00,0x08]
 
 ds_write_b128 v2, v[4:7]
 // NOSI: error: instruction not supported on this GPU
 // CI: ds_write_b128 v2, v[4:7] ; encoding: [0x00,0x00,0x7c,0xdb,0x02,0x04,0x00,0x00]
 // VI:   ds_write_b128 v2, v[4:7] ; encoding: [0x00,0x00,0xbe,0xd9,0x02,0x04,0x00,0x00]
+
+ds_nop
+// NOSI: error: instruction not supported on this GPU
+// CI: ds_nop ; encoding: [0x00,0x00,0x50,0xd8,0x00,0x00,0x00,0x00]
+// VI: ds_nop ; encoding: [0x00,0x00,0x28,0xd8,0x00,0x00,0x00,0x00]