[X86][btver2] PR31902: Fix a crash in combineOrCmpEqZeroToCtlzSrl under fast math.

[pgousseau]

Summary

In combineOrCmpEqZeroToCtlzSrl, replace "getConstantOperand == 0" by "isNullConstant" to account for floating point constants.

[andreadb]

Basically, there is no guarantee that N->getOperand(1) is an integer value.

LGTM.

[spatel]

test/CodeGen/X86/lzcnt-zext-cmp.ll

4–7 ↗

(On Diff #87785)

An opportunity to make this easier to read (as a separate patch): add a common prefix for all runs ("ALL") and rerun the script. That way it will be obvious which tests expect no transformation.

[pgousseau]

test/CodeGen/X86/lzcnt-zext-cmp.ll

4–7 ↗

(On Diff #87785)

Makes sense, will have a look!

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

if (!N->hasOneUse() || !N->getSimpleValueType(0).bitsGE(MVT::i32) ||
       !isORCandidate(N->getOperand(0)))
     return SDValue();
 
   // Check the node matches: setcc(eq, cmp 0)
   auto isSetCCCandidate = [](SDValue N) {
     return N->getOpcode() == X86ISD::SETCC && N->hasOneUse() &&
            X86::CondCode(N->getConstantOperandVal(0)) == X86::COND_E &&
            N->getOperand(1).getOpcode() == X86ISD::CMP &&
-           N->getOperand(1).getConstantOperandVal(1) == 0 &&
+           isNullConstant(N->getOperand(1).getOperand(1)) &&
            N->getOperand(1).getValueType().bitsGE(MVT::i32);
   };
 
   SDNode *OR = N->getOperand(0).getNode();
   SDValue LHS = OR->getOperand(0);
   SDValue RHS = OR->getOperand(1);
 
   // Save nodes matching or(or, setcc(eq, cmp 0)).

llvm/trunk/test/CodeGen/X86/lzcnt-zext-cmp.ll

entry:
   %b.sroa.0.0.insert.ext = zext i64 %b.coerce0 to i128
   %b.sroa.0.0.insert.insert = or i128 %b.sroa.2.0.insert.shift, %b.sroa.0.0.insert.ext
   %cmp = icmp eq i128 %a.sroa.0.0.insert.insert, 0
   %cmp3 = icmp eq i128 %b.sroa.0.0.insert.insert, 0
   %0 = or i1 %cmp, %cmp3
   %lor.ext = zext i1 %0 to i32
   ret i32 %lor.ext
 }
+
+; PR31902 Fix a crash in combineOrCmpEqZeroToCtlzSrl under fast math.
+define i32 @test_zext_cmp11(double %a, double %b) "no-nans-fp-math"="true" {
+; CHECK-LABEL: test_zext_cmp11:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT:    vucomisd %xmm2, %xmm0
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    vucomisd %xmm2, %xmm1
+; CHECK-NEXT:    sete %cl
+; CHECK-NEXT:    orb %al, %cl
+; CHECK-NEXT:    movzbl %cl, %eax
+; CHECK-NEXT:    retq
+;
+; NOFASTLZCNT-LABEL: test_zext_cmp11:
+; NOFASTLZCNT:       # BB#0: # %entry
+; NOFASTLZCNT-NEXT:    vxorps %xmm2, %xmm2, %xmm2
+; NOFASTLZCNT-NEXT:    vucomisd %xmm2, %xmm0
+; NOFASTLZCNT-NEXT:    sete %al
+; NOFASTLZCNT-NEXT:    vucomisd %xmm2, %xmm1
+; NOFASTLZCNT-NEXT:    sete %cl
+; NOFASTLZCNT-NEXT:    orb %al, %cl
+; NOFASTLZCNT-NEXT:    movzbl %cl, %eax
+; NOFASTLZCNT-NEXT:    retq
+entry:
+  %cmp = fcmp fast oeq double %a, 0.000000e+00
+  %cmp1 = fcmp fast oeq double %b, 0.000000e+00
+  %0 = or i1 %cmp, %cmp1
+  %conv = zext i1 %0 to i32
+  ret i32 %conv
+}