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[PowerPC] pseudo instruction EH_SjLj_LongJmp64 requires G8RC_NOX0 register
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Authored by lei on Jan 30 2017, 9:37 AM.

Details

Summary

Expansion of the pseudo instruction EH_SjLj_LongJmp64 resulted in the LD instruction receiving a G8RC class register as opposed to the expected G8RC_NOX0 register.

Definition of MIoperandInfo for memr is ptr_rc. From what I can tell memr is used with:

SjLj pseudo-instructions
LXVL/LXVLL vector loads
STXVL/STXVLL vector stores
Based on the ISA, the vector instructions and the LD/LWZ, that the SjLj pseudo-instructions translates to, all require G8RC_NO0X class registers for RA.

Diff Detail

Repository
rL LLVM

Event Timeline

lei created this revision.Jan 30 2017, 9:37 AM
nemanjai added inline comments.Jan 30 2017, 10:28 AM
lib/Target/PowerPC/PPCInstrInfo.td
774 ↗(On Diff #86303)

Typo. G8RC_NOX0

hfinkel accepted this revision.Jan 30 2017, 9:21 PM

Test case needs some cleanup, otherwise LGTM.

test/CodeGen/PowerPC/sjlj_no0x.ll
31 ↗(On Diff #86303)

Remove unnecessary attributes.

38 ↗(On Diff #86303)

Remove unnecessary metadata.

This revision is now accepted and ready to land.Jan 30 2017, 9:21 PM
lei marked 3 inline comments as done.Jan 31 2017, 10:17 AM
lei added inline comments.
lib/Target/PowerPC/PPCInstrInfo.td
774 ↗(On Diff #86303)

fixed

test/CodeGen/PowerPC/sjlj_no0x.ll
31 ↗(On Diff #86303)

done

38 ↗(On Diff #86303)

done

This revision was automatically updated to reflect the committed changes.