[ARM] Enable v8.3-A complex instruction support

[samparker]

Summary

Adding AArch32 assembly and disassembly support for the complex instructions which have been introduced as a part of the ARMv8.3-A architecture.

[rengolin]

I'm going to be a bit redundant here, but is there a manual we can use to check?

[rengolin]

In sync with D29272, no docs, no review.

lib/Target/ARM/ARMInstrFormats.td

 def N2RegVShLFrm  : Format<35>;
 def N2RegVShRFrm  : Format<36>;
 def N3RegFrm      : Format<37>;
 def N3RegVShFrm   : Format<38>;
 def NVExtFrm      : Format<39>;
 def NVMulSLFrm    : Format<40>;
 def NVTBLFrm      : Format<41>;
 def DPSoRegImmFrm  : Format<42>;
+def N3RegCplxFrm  : Format<43>;
 
 // Misc flags.
 
 // The instruction has an Rn register operand.
 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
 // it doesn't have a Rn operand.
 class UnaryDP    { bit isUnaryDataProc = 1; }
 

 // The same alias classes using AsmPseudo instead, for the more complex
 // stuff in NEON that InstAlias can't quite handle.
 // Note that we can't use anonymous defm references here like we can
 // above, as we care about the ultimate instruction enum names generated, unlike
 // for instalias defs.
 class NEONDataTypeAsmPseudoInst<string opc, string dt, string asm, dag iops> :
   AsmPseudoInst<!strconcat(opc, dt, "\t", asm), iops>, Requires<[HasNEON]>;
 
+// Extension of NEON 3-vector data processing instructions in coprocessor 8
+// encoding space, introduced in ARMv8.3-A.
+class N3VCP8<bits<2> op24_23, bits<2> op21_20, bit op6, bit op4,
+             dag oops, dag iops, InstrItinClass itin,
+             string opc, string dt, string asm, string cstr, list<dag> pattern>
+  : NeonInp<oops, iops, AddrModeNone, IndexModeNone, N3RegCplxFrm, itin, opc, dt, asm, cstr, pattern> {
+  bits<5> Vd;
+  bits<5> Vn;
+  bits<5> Vm;
+
+  let DecoderNamespace = "VFPV8";
+  // These have the same encodings in ARM and Thumb2
+  let PostEncoderMethod = "";
+
+  let Inst{31-25} = 0b1111110;
+  let Inst{24-23} = op24_23;
+  let Inst{22}    = Vd{4};
+  let Inst{21-20} = op21_20;
+  let Inst{19-16} = Vn{3-0};
+  let Inst{15-12} = Vd{3-0};
+  let Inst{11-8}  = 0b1000;
+  let Inst{7}     = Vn{4};
+  let Inst{6}     = op6;
+  let Inst{5}     = Vm{4};
+  let Inst{4}     = op4;
+  let Inst{3-0}   = Vm{3-0};
+}
+
+// Extension of NEON 2-vector-and-scalar data processing instructions in
+// coprocessor 8 encoding space, introduced in ARMv8.3-A.
+class N3VLaneCP8<bit op23, bits<2> op21_20, bit op6, bit op4,
+             dag oops, dag iops, InstrItinClass itin,
+             string opc, string dt, string asm, string cstr, list<dag> pattern>
+  : NeonInp<oops, iops, AddrModeNone, IndexModeNone, N3RegCplxFrm, itin, opc, dt, asm, cstr, pattern> {
+  bits<5> Vd;
+  bits<5> Vn;
+  bits<5> Vm;
+
+  let DecoderNamespace = "VFPV8";
+  // These have the same encodings in ARM and Thumb2
+  let PostEncoderMethod = "";
+
+  let Inst{31-24} = 0b11111110;
+  let Inst{23}    = op23;
+  let Inst{22}    = Vd{4};
+  let Inst{21-20} = op21_20;
+  let Inst{19-16} = Vn{3-0};
+  let Inst{15-12} = Vd{3-0};
+  let Inst{11-8}  = 0b1000;
+  let Inst{7}     = Vn{4};
+  let Inst{6}     = op6;
+  // Bit 5 set by sub-classes
+  let Inst{4}     = op4;
+  let Inst{3-0}   = Vm{3-0};
+}
+
+// Operand types for complex instructions
+def ComplexRotationOperand : AsmOperandClass {
+  let Name = "ComplexRotation";
+  let DiagnosticType = "InvalidComplexRotation";
+}
+def complexrotateop : Operand<i32> {
+  let ParserMatchClass = ComplexRotationOperand;
+  let PrintMethod = "printComplexRotationOp";
+}
+def ComplexRotationOddOperand : AsmOperandClass {
+  let Name = "ComplexRotationOdd";
+  let DiagnosticType = "InvalidComplexRotationOdd";
+  let SuperClasses = [ComplexRotationOperand];
+}
+def complexrotateopodd : Operand<i32> {
+  let ParserMatchClass = ComplexRotationOddOperand;
+  let PrintMethod = "printComplexRotationOpOdd";
+}
+
 // Data type suffix token aliases. Implements Table A7-3 in the ARM ARM.
 def : TokenAlias<".s8", ".i8">;
 def : TokenAlias<".u8", ".i8">;
 def : TokenAlias<".s16", ".i16">;
 def : TokenAlias<".u16", ".i16">;
 def : TokenAlias<".s32", ".i32">;
 def : TokenAlias<".u32", ".i32">;
 def : TokenAlias<".s64", ".i64">;

lib/Target/ARM/ARMInstrNEON.td

 def nImmSplatI64 : Operand<i32> {
   let PrintMethod = "printNEONModImmOperand";
   let ParserMatchClass = nImmSplatI64AsmOperand;
 }
 
 def VectorIndex8Operand  : AsmOperandClass { let Name = "VectorIndex8"; }
 def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
 def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; }
+def VectorIndex64Operand : AsmOperandClass { let Name = "VectorIndex64"; }
 def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{
   return ((uint64_t)Imm) < 8;
 }]> {
   let ParserMatchClass = VectorIndex8Operand;
   let PrintMethod = "printVectorIndex";
   let MIOperandInfo = (ops i32imm);
 }
 def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{
   return ((uint64_t)Imm) < 4;
 }]> {
   let ParserMatchClass = VectorIndex16Operand;
   let PrintMethod = "printVectorIndex";
   let MIOperandInfo = (ops i32imm);
 }
 def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
   return ((uint64_t)Imm) < 2;
 }]> {
   let ParserMatchClass = VectorIndex32Operand;
   let PrintMethod = "printVectorIndex";
   let MIOperandInfo = (ops i32imm);
 }
+def VectorIndex64 : Operand<i32>, ImmLeaf<i32, [{
+  return ((uint64_t)Imm) < 1;
+}]> {
+  let ParserMatchClass = VectorIndex64Operand;
+  let PrintMethod = "printVectorIndex";
+  let MIOperandInfo = (ops i32imm);
+}
 
 // Register list of one D register.
 def VecListOneDAsmOperand : AsmOperandClass {
   let Name = "VecListOneD";
   let ParserMethod = "parseVectorList";
   let RenderMethod = "addVecListOperands";
 }
 def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {

           Requires<[HasVFP4]>;
 def : Pat<(v2f32 (fma (fneg DPR:$Vn), DPR:$Vm, DPR:$src1)),
           (VFMSfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
       Requires<[HasVFP4]>;
 def : Pat<(v4f32 (fma (fneg QPR:$Vn), QPR:$Vm, QPR:$src1)),
           (VFMSfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
       Requires<[HasVFP4]>;
 
+// ARMv8.3 complex operations
+class BaseN3VCP8ComplexTied<bit op21, bit op4, bit s, bit q, InstrItinClass itin,
+                            dag oops, dag iops, string opc, string dt, list<dag> pattern>
+  : N3VCP8<{?,?}, {op21,s}, q, op4, oops,
+           iops, itin, opc, dt, "$Vd, $Vn, $Vm, $rot", "$src1 = $Vd", pattern> {
+  bits<2> rot;
+  let Inst{24-23} = rot;
+}
+
+class BaseN3VCP8ComplexOdd<bit op23, bit op21, bit op4, bit s, bit q, InstrItinClass itin,
+                            dag oops, dag iops, string opc, string dt, list<dag> pattern>
+  : N3VCP8<{?,op23}, {op21,s}, q, op4, oops,
+           iops, itin, opc, dt, "$Vd, $Vn, $Vm, $rot", "", pattern> {
+  bits<1> rot;
+  let Inst{24} = rot;
+}
+
+class BaseN3VCP8ComplexTiedLane32<bit op4, bit s, bit q, InstrItinClass itin,
+                            dag oops, dag iops, string opc, string dt, list<dag> pattern>
+  : N3VLaneCP8<s, {?,?}, q, op4, oops, iops, itin, opc, dt, "$Vd, $Vn, $Vm$lane, $rot", "$src1 = $Vd", pattern> {
+  bits<2> rot;
+  bit lane;
+
+  let Inst{21-20} = rot;
+  let Inst{5} = lane;
+}
+class BaseN3VCP8ComplexTiedLane64<bit op4, bit s, bit q, InstrItinClass itin,
+                            dag oops, dag iops, string opc, string dt, list<dag> pattern>
+  : N3VLaneCP8<s, {?,?}, q, op4, oops, iops, itin, opc, dt, "$Vd, $Vn, $Vm$lane, $rot", "$src1 = $Vd", pattern> {
+  bits<2> rot;
+  bit lane;
+
+  let Inst{21-20} = rot;
+  let Inst{5} = Vm{4};
+  // This is needed because the lane operand does not have any bits in the
+  // encoding (it only has one possible value), so we need to manually set it
+  // to it's default value.
+  let DecoderMethod = "DecodeNEONComplexLane64Instruction";
+}
+
+multiclass N3VCP8ComplexTied<bit op21, bit op4,
+                       string OpcodeStr, SDPatternOperator Op> {
+  let Predicates = [HasNEON,HasV8_3a,HasFullFP16] in {
+  def v4f16 : BaseN3VCP8ComplexTied<op21, op4, 0, 0, IIC_VMACD, (outs DPR:$Vd),
+                                    (ins DPR:$src1, DPR:$Vn, DPR:$Vm, complexrotateop:$rot),
+                                    OpcodeStr, "f16", []>;
+  def v8f16 : BaseN3VCP8ComplexTied<op21, op4, 0, 1, IIC_VMACQ, (outs QPR:$Vd),
+                                    (ins QPR:$src1, QPR:$Vn, QPR:$Vm, complexrotateop:$rot),
+                                    OpcodeStr, "f16", []>;
+  }
+  let Predicates = [HasNEON,HasV8_3a] in {
+  def v2f32 : BaseN3VCP8ComplexTied<op21, op4, 1, 0, IIC_VMACD, (outs DPR:$Vd),
+                                    (ins DPR:$src1, DPR:$Vn, DPR:$Vm, complexrotateop:$rot),
+                                    OpcodeStr, "f32", []>;
+  def v4f32 : BaseN3VCP8ComplexTied<op21, op4, 1, 1, IIC_VMACQ, (outs QPR:$Vd),
+                                    (ins QPR:$src1, QPR:$Vn, QPR:$Vm, complexrotateop:$rot),
+                                    OpcodeStr, "f32", []>;
+  }
+}
+
+multiclass N3VCP8ComplexOdd<bit op23, bit op21, bit op4,
+                       string OpcodeStr, SDPatternOperator Op> {
+  let Predicates = [HasNEON,HasV8_3a,HasFullFP16] in {
+  def v4f16 : BaseN3VCP8ComplexOdd<op23, op21, op4, 0, 0, IIC_VMACD, (outs DPR:$Vd),
+                                    (ins DPR:$Vn, DPR:$Vm, complexrotateopodd:$rot),
+                                    OpcodeStr, "f16", []>;
+  def v8f16 : BaseN3VCP8ComplexOdd<op23, op21, op4, 0, 1, IIC_VMACQ, (outs QPR:$Vd),
+                                    (ins QPR:$Vn, QPR:$Vm, complexrotateopodd:$rot),
+                                    OpcodeStr, "f16", []>;
+  }
+  let Predicates = [HasNEON,HasV8_3a] in {
+  def v2f32 : BaseN3VCP8ComplexOdd<op23, op21, op4, 1, 0, IIC_VMACD, (outs DPR:$Vd),
+                                    (ins DPR:$Vn, DPR:$Vm, complexrotateopodd:$rot),
+                                    OpcodeStr, "f32", []>;
+  def v4f32 : BaseN3VCP8ComplexOdd<op23, op21, op4, 1, 1, IIC_VMACQ, (outs QPR:$Vd),
+                                    (ins QPR:$Vn, QPR:$Vm, complexrotateopodd:$rot),
+                                    OpcodeStr, "f32", []>;
+  }
+}
+
+// These instructions index by pairs of lanes, so the VectorIndexes are twice
+// as wide as the data types.
+multiclass N3VCP8ComplexTiedLane<bit op4, string OpcodeStr, SDPatternOperator Op> {
+  let Predicates = [HasNEON,HasV8_3a,HasFullFP16] in {
+  def v4f16_indexed : BaseN3VCP8ComplexTiedLane32<op4, 0, 0, IIC_VMACD, (outs DPR:$Vd),
+                                    (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, complexrotateop:$rot),
+                                    OpcodeStr, "f16", []>;
+  def v8f16_indexed : BaseN3VCP8ComplexTiedLane32<op4, 0, 1, IIC_VMACQ, (outs QPR:$Vd),
+                                    (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane, complexrotateop:$rot),
+                                    OpcodeStr, "f16", []>;
+  }
+  let Predicates = [HasNEON,HasV8_3a] in {
+  def v2f32_indexed : BaseN3VCP8ComplexTiedLane64<op4, 1, 0, IIC_VMACD, (outs DPR:$Vd),
+                                    (ins DPR:$src1, DPR:$Vn, DPR:$Vm, VectorIndex64:$lane, complexrotateop:$rot),
+                                    OpcodeStr, "f32", []>;
+  def v4f32_indexed : BaseN3VCP8ComplexTiedLane64<op4, 1, 1, IIC_VMACQ, (outs QPR:$Vd),
+                                    (ins QPR:$src1, QPR:$Vn, DPR:$Vm, VectorIndex64:$lane, complexrotateop:$rot),
+                                    OpcodeStr, "f32", []>;
+  }
+}
+
+defm VCMLA : N3VCP8ComplexTied<1, 0, "vcmla", null_frag>;
+defm VCADD : N3VCP8ComplexOdd<1, 0, 0, "vcadd", null_frag>;
+defm VCMLA : N3VCP8ComplexTiedLane<0, "vcmla", null_frag>;
+
 // Vector Subtract Operations.
 
 //   VSUB     : Vector Subtract (integer and floating-point)
 defm VSUB     : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
                          "vsub", "i", sub, 0>;
 def  VSUBfd   : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
                      v2f32, v2f32, fsub, 0>;
 def  VSUBfq   : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

   bool isVectorIndex16() const {
     if (Kind != k_VectorIndex) return false;
     return VectorIndex.Val < 4;
   }
   bool isVectorIndex32() const {
     if (Kind != k_VectorIndex) return false;
     return VectorIndex.Val < 2;
   }
+  bool isVectorIndex64() const {
+    if (Kind != k_VectorIndex) return false;
+    return VectorIndex.Val < 1;
+  }
 
   bool isNEONi8splat() const {
     if (!isImm()) return false;
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     // Must be a constant.
     if (!CE) return false;
     int64_t Value = CE->getValue();
     // i8 value splatted across 8 bytes. The immediate is just the 8 byte

     if (!CE) return false;
     uint64_t Value = CE->getValue();
     // i64 value with each byte being either 0 or 0xff.
     for (unsigned i = 0; i < 8; ++i, Value >>= 8)
       if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
     return true;
   }
 
+  bool isComplexRotation() const {
+    if (!isImm()) return false;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    if (!CE) return false;
+    int64_t Value = CE->getValue();
+    return Value >= 0 && Value <= 270 && Value % 90 == 0;
+  }
+
+  bool isComplexRotationOdd() const {
+    if (!isImm()) return false;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    if (!CE) return false;
+    int64_t Value = CE->getValue();
+    return Value == 90 || Value == 270;
+  }
+
   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
     // Add as immediates when possible.  Null MCExpr = 0.
     if (!Expr)
       Inst.addOperand(MCOperand::createImm(0));
     else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
       Inst.addOperand(MCOperand::createImm(CE->getValue()));
     else
       Inst.addOperand(MCOperand::createExpr(Expr));

     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
   }
 
   void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
   }
 
+  void addVectorIndex64Operands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createImm(getVectorIndex()));
+  }
+
   void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     // The immediate encodes the type of constant as well as the value.
     // Mask in that this is an i8 splat.
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
   }
 

     uint64_t Value = CE->getValue();
     unsigned Imm = 0;
     for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
       Imm |= (Value & 1) << i;
     }
     Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
   }
 
+  void addComplexRotationOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    unsigned Value = CE->getValue();
+    Inst.addOperand(MCOperand::createImm(Value / 90));
+  }
+
+  void addComplexRotationOddOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    unsigned Value = CE->getValue();
+    Inst.addOperand(MCOperand::createImm((Value - 90) / 180));
+  }
+
   void print(raw_ostream &OS) const override;
 
   static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
     auto Op = make_unique<ARMOperand>(k_ITCondMask);
     Op->ITMask.Mask = Mask;
     Op->StartLoc = S;
     Op->EndLoc = S;
     return Op;

       Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
       Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
       Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
       Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
       Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
       Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
       Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
       Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx" ||
-      Mnemonic == "bxns"  || Mnemonic == "blxns")
+      Mnemonic == "bxns"  || Mnemonic == "blxns" || Mnemonic == "vcmla" ||
+      Mnemonic == "vcadd")
     return Mnemonic;
 
   // First, split out any predication code. Ignore mnemonics we know aren't
   // predicated but do have a carry-set and so weren't caught above.
   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
       Mnemonic != "sbcs" && Mnemonic != "rscs") {

       Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
       Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" ||
       Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" ||
       Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" ||
       Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||
       Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||
       Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
       (FullInst.startswith("vmull") && FullInst.endswith(".p64")) ||
-      Mnemonic == "vmovx" || Mnemonic == "vins") {
+      Mnemonic == "vmovx" || Mnemonic == "vins" || Mnemonic == "vcmla" ||
+      Mnemonic == "vcadd") {
     // These mnemonics are never predicable
     CanAcceptPredicationCode = false;
   } else if (!isThumb()) {
     // Some instructions are only predicable in Thumb mode
     CanAcceptPredicationCode =
         Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
         Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
         Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&

         return Error(ErrorLoc, "alignment must be 64 or omitted");
       case Match_AlignedMemoryRequires64or128:
       case Match_DupAlignedMemoryRequires64or128:
         return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
       case Match_AlignedMemoryRequires64or128or256:
         return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
     }
   }
+  case Match_InvalidComplexRotation:
+      return Error(IDLoc, "complex rotation must be 0, 90, 180 or 270");
+  case Match_InvalidComplexRotationOdd:
+      return Error(IDLoc, "complex rotation must be 90 or 270");
   }
 
   llvm_unreachable("Implement any new match types added!");
 }
 
 /// parseDirective parses the arm specific directives
 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
   const MCObjectFileInfo::Environment Format =

lib/Target/ARM/Disassembler/ARMDisassembler.cpp

 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
                                 uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
                                 uint64_t Address, const void *Decoder);
-
+static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
+                                                       unsigned Val,
+                                                       uint64_t Address,
+                                                       const void *Decoder);
 
 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,

     return MCDisassembler::Fail;
   if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(64 - imm));
 
   return S;
 }
 
+static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
+                                                       unsigned Insn,
+                                                       uint64_t Address,
+                                                       const void *Decoder) {
+  unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
+  Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
+  unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0);
+  Vn |= (fieldFromInstruction(Insn, 7, 1) << 4);
+  unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
+  Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
+  unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0);
+  unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0);
+
+  DecodeStatus S = MCDisassembler::Success;
+
+  auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass;
+
+  if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
+    return MCDisassembler::Fail;
+  // The lane index does not have any bits in the encoding, because it can only
+  // be 0.
+  Inst.addOperand(MCOperand::createImm(0));
+  Inst.addOperand(MCOperand::createImm(rotate));
+
+  return S;
+}
+
 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
                                 uint64_t Address, const void *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Val, 16, 4);
   unsigned Rt = fieldFromInstruction(Val, 12, 4);
   unsigned Rm = fieldFromInstruction(Val, 0, 4);
   Rm |= (fieldFromInstruction(Val, 23, 1) << 4);

lib/Target/ARM/InstPrinter/ARMInstPrinter.h

                                           raw_ostream &O);
   void printVectorListFourSpacedAllLanes(const MCInst *MI, unsigned OpNum,
                                          const MCSubtargetInfo &STI,
                                          raw_ostream &O);
   void printVectorListThreeSpaced(const MCInst *MI, unsigned OpNum,
                                   const MCSubtargetInfo &STI, raw_ostream &O);
   void printVectorListFourSpaced(const MCInst *MI, unsigned OpNum,
                                  const MCSubtargetInfo &STI, raw_ostream &O);
+  void printComplexRotationOp(const MCInst *MI, unsigned OpNum,
+                              const MCSubtargetInfo &STI, raw_ostream &O);
+  void printComplexRotationOpOdd(const MCInst *MI, unsigned OpNum,
+                                 const MCSubtargetInfo &STI, raw_ostream &O);
 };
 
 } // end namespace llvm
 
 #endif

lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp

   O << ", ";
   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
   O << ", ";
   printRegName(O, MI->getOperand(OpNum).getReg() + 4);
   O << ", ";
   printRegName(O, MI->getOperand(OpNum).getReg() + 6);
   O << "}";
 }
+
+void ARMInstPrinter::printComplexRotationOp(const MCInst *MI, unsigned OpNo,
+                                            const MCSubtargetInfo &STI,
+                                            raw_ostream &O) {
+  unsigned Val = MI->getOperand(OpNo).getImm();
+  O << "#" << Val * 90;
+}
+
+void ARMInstPrinter::printComplexRotationOpOdd(const MCInst *MI, unsigned OpNo,
+                                               const MCSubtargetInfo &STI,
+                                               raw_ostream &O) {
+  unsigned Val = MI->getOperand(OpNo).getImm();
+  O << "#" << (Val * 180) + 90;
+}

lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h

     NVDupLnFrm    = 34 << FormShift,
     N2RegVShLFrm  = 35 << FormShift,
     N2RegVShRFrm  = 36 << FormShift,
     N3RegFrm      = 37 << FormShift,
     N3RegVShFrm   = 38 << FormShift,
     NVExtFrm      = 39 << FormShift,
     NVMulSLFrm    = 40 << FormShift,
     NVTBLFrm      = 41 << FormShift,
+    N3RegCPlxFrm  = 43 << FormShift,
 
     //===------------------------------------------------------------------===//
     // Misc flags.
 
     // UnaryDP - Indicates this is a unary data processing instruction, i.e.
     // it doesn't have a Rn operand.
     UnaryDP       = 1 << 13,
 

test/MC/ARM/neon-complex.s

+// RUN: not llvm-mc -triple thumb-none-linux-gnu -mattr=+v8.3a,+neon,+fullfp16 -show-encoding < %s 2>%t | FileCheck %s --check-prefix=THUMB --check-prefix=FP16-THUMB
+// RUN: FileCheck --check-prefix=STDERR <%t %s
+// RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.3a,+neon,+fullfp16 -show-encoding < %s 2>%t | FileCheck %s --check-prefix=ARM --check-prefix=FP16-ARM
+// RUN: FileCheck --check-prefix=STDERR <%t %s
+
+// RUN: not llvm-mc -triple thumb-none-linux-gnu -mattr=+v8.3a,+neon,-fullfp16 -show-encoding < %s 2>%t | FileCheck %s --check-prefix=THUMB
+// RUN: FileCheck --check-prefix=STDERR --check-prefix=NO-FP16-STDERR <%t %s
+// RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.3a,+neon,-fullfp16 -show-encoding < %s 2>%t | FileCheck %s --check-prefix=ARM
+// RUN: FileCheck --check-prefix=STDERR --check-prefix=NO-FP16-STDERR <%t %s
+
+// RUN: not llvm-mc -triple thumb-none-linux-gnu -mattr=+v8.2a,+neon,+fullfp16 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=V82A
+// RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.2a,+neon,+fullfp16 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=V82A
+
+/* ==== VCMLA vector ==== */
+
+// Valid types
+  vcmla.f16 d0, d1, d2, #0
+// FP16-ARM: vcmla.f16       d0, d1, d2, #0  @ encoding: [0x02,0x08,0x21,0xfc]
+// FP16-THUMB: vcmla.f16       d0, d1, d2, #0  @ encoding: [0x21,0xfc,0x02,0x08]
+// NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: full half-float
+// V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires:
+  vcmla.f16 q0, q1, q2, #0
+// FP16-ARM: vcmla.f16       q0, q1, q2, #0  @ encoding: [0x44,0x08,0x22,0xfc]
+// FP16-THUMB: vcmla.f16       q0, q1, q2, #0  @ encoding: [0x22,0xfc,0x44,0x08]
+// NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: full half-float
+// V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires:
+  vcmla.f32 d0, d1, d2, #0
+// ARM: vcmla.f32       d0, d1, d2, #0  @ encoding: [0x02,0x08,0x31,0xfc]
+// THUMB: vcmla.f32       d0, d1, d2, #0  @ encoding: [0x31,0xfc,0x02,0x08]
+// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires:
+  vcmla.f32 q0, q1, q2, #0
+// ARM: vcmla.f32       q0, q1, q2, #0  @ encoding: [0x44,0x08,0x32,0xfc]
+// THUMB: vcmla.f32       q0, q1, q2, #0  @ encoding: [0x32,0xfc,0x44,0x08]
+// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires:
+
+// Valid rotations
+  vcmla.f32 d0, d1, d2, #90
+// ARM: vcmla.f32       d0, d1, d2, #90 @ encoding: [0x02,0x08,0xb1,0xfc]
+// THUMB: vcmla.f32       d0, d1, d2, #90 @ encoding: [0xb1,0xfc,0x02,0x08]
+// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires:
+  vcmla.f32 d0, d1, d2, #180
+// ARM: vcmla.f32       d0, d1, d2, #180 @ encoding: [0x02,0x08,0x31,0xfd]
+// THUMB: vcmla.f32       d0, d1, d2, #180 @ encoding: [0x31,0xfd,0x02,0x08]
+// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires:
+  vcmla.f32 d0, d1, d2, #270
+// ARM: vcmla.f32       d0, d1, d2, #270 @ encoding: [0x02,0x08,0xb1,0xfd]
+// THUMB: vcmla.f32       d0, d1, d2, #270 @ encoding: [0xb1,0xfd,0x02,0x08]
+// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires:
+
+// Invalid rotations
+  vcmla.f32 d0, d1, d2, #-90
+// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270
+  vcmla.f32 d0, d1, d2, #1
+// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270
+  vcmla.f32 d0, d1, d2, #360
+// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270
+
+/* ==== VCADD vector ==== */
+
+// Valid types
+  vcadd.f16 d0, d1, d2, #90
+// FP16-ARM: vcadd.f16       d0, d1, d2, #90 @ encoding: [0x02,0x08,0x81,0xfc]
+// FP16-THUMB: vcadd.f16       d0, d1, d2, #90 @ encoding: [0x81,0xfc,0x02,0x08]
+// NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: full half-float
+// V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires:
+  vcadd.f16 q0, q1, q2, #90
+// FP16-ARM: vcadd.f16       q0, q1, q2, #90 @ encoding: [0x44,0x08,0x82,0xfc]
+// FP16-THUMB: vcadd.f16       q0, q1, q2, #90 @ encoding: [0x82,0xfc,0x44,0x08]
+// NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: full half-float
+// V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires:
+  vcadd.f32 d0, d1, d2, #90
+// ARM: vcadd.f32       d0, d1, d2, #90 @ encoding: [0x02,0x08,0x91,0xfc]
+// THUMB: vcadd.f32       d0, d1, d2, #90 @ encoding: [0x91,0xfc,0x02,0x08]
+// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires:
+  vcadd.f32 q0, q1, q2, #90
+// ARM: vcadd.f32       q0, q1, q2, #90 @ encoding: [0x44,0x08,0x92,0xfc]
+// THUMB: vcadd.f32       q0, q1, q2, #90 @ encoding: [0x92,0xfc,0x44,0x08]
+// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires:
+
+// Valid rotations
+  vcadd.f32 d0, d1, d2, #270
+// ARM: vcadd.f32       d0, d1, d2, #270 @ encoding: [0x02,0x08,0x91,0xfd]
+// THUMB: vcadd.f32       d0, d1, d2, #270 @ encoding: [0x91,0xfd,0x02,0x08]
+// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires:
+
+// Invalid rotations
+  vcadd.f32 d0, d1, d2, #0
+// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270
+  vcadd.f32 d0, d1, d2, #180
+// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270
+  vcadd.f32 d0, d1, d2, #-90
+// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270
+  vcadd.f32 d0, d1, d2, #1
+// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270
+  vcadd.f32 d0, d1, d2, #360
+// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270
+
+
+/* ==== VCMLA indexed ==== */
+
+// Valid types
+  vcmla.f16 d0, d1, d2[0], #0
+// FP16-ARM: vcmla.f16       d0, d1, d2[0], #0 @ encoding: [0x02,0x08,0x01,0xfe]
+// FP16-THUMB: vcmla.f16       d0, d1, d2[0], #0 @ encoding: [0x01,0xfe,0x02,0x08]
+// NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: full half-float
+// V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires:
+  vcmla.f16 q0, q1, d2[0], #0
+// FP16-ARM: vcmla.f16       q0, q1, d2[0], #0 @ encoding: [0x42,0x08,0x02,0xfe]
+// FP16-THUMB: vcmla.f16       q0, q1, d2[0], #0 @ encoding: [0x02,0xfe,0x42,0x08]
+// NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: full half-float
+// V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires:
+  vcmla.f32 d0, d1, d2[0], #0
+// ARM: vcmla.f32       d0, d1, d2[0], #0 @ encoding: [0x02,0x08,0x81,0xfe]
+// THUMB: vcmla.f32       d0, d1, d2[0], #0 @ encoding: [0x81,0xfe,0x02,0x08]
+// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires:
+  vcmla.f32 q0, q1, d2[0], #0
+// ARM: vcmla.f32       q0, q1, d2[0], #0 @ encoding: [0x42,0x08,0x82,0xfe]
+// THUMB: vcmla.f32       q0, q1, d2[0], #0 @ encoding: [0x82,0xfe,0x42,0x08]
+// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires:
+
+// Valid rotations
+  vcmla.f32 d0, d1, d2[0], #90
+// ARM: vcmla.f32       d0, d1, d2[0], #90 @ encoding: [0x02,0x08,0x91,0xfe]
+// THUMB: vcmla.f32       d0, d1, d2[0], #90 @ encoding: [0x91,0xfe,0x02,0x08]
+// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires:
+  vcmla.f32 d0, d1, d2[0], #180
+// ARM: vcmla.f32       d0, d1, d2[0], #180 @ encoding: [0x02,0x08,0xa1,0xfe]
+// THUMB: vcmla.f32       d0, d1, d2[0], #180 @ encoding: [0xa1,0xfe,0x02,0x08]
+// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires:
+  vcmla.f32 d0, d1, d2[0], #270
+// ARM: vcmla.f32       d0, d1, d2[0], #270 @ encoding: [0x02,0x08,0xb1,0xfe]
+// THUMB: vcmla.f32       d0, d1, d2[0], #270 @ encoding: [0xb1,0xfe,0x02,0x08]
+// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires:
+
+// Invalid rotations
+  vcmla.f32 d0, d1, d2[0], #-90
+// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270
+  vcmla.f32 d0, d1, d2[0], #1
+// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270
+  vcmla.f32 d0, d1, d2[0], #360
+// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270
+
+// Valid indices
+  vcmla.f16 d0, d1, d2[1], #0
+// FP16-ARM: vcmla.f16       d0, d1, d2[1], #0 @ encoding: [0x22,0x08,0x01,0xfe]
+// FP16-THUMB: vcmla.f16       d0, d1, d2[1], #0 @ encoding: [0x01,0xfe,0x22,0x08]
+// V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires:
+
+// Invalid indices
+// FIXME: These error messages are emitted because the index operand is not
+// valid as a rotation, so they are a bit unintuitive. Can we do better?
+  vcmla.f16 d0, d1, d2[2], #0
+// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270
+  vcmla.f32 d0, d1, d2[1], #0
+// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270

test/MC/Disassembler/ARM/neon-complex-arm.txt

+# RUN:     llvm-mc -triple armv8a -mattr=+v8.3a,+neon,+fullfp16 -disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP16
+# RUN: not llvm-mc -triple armv8a -mattr=+v8.2a,+neon,+fullfp16 -disassemble < %s 2>&1 | FileCheck %s --check-prefix=MISSING --check-prefix=MISSING-FP16
+# RUN: not llvm-mc -triple armv8a -mattr=+v8.3a,-neon,+fullfp16 -disassemble < %s 2>&1 | FileCheck %s --check-prefix=MISSING --check-prefix=MISSING-FP16
+# RUN: not llvm-mc -triple armv8a -mattr=+v8.3a,+neon,-fullfp16 -disassemble < %s 2>%t | FileCheck %s --check-prefix=CHECK
+# RUN: FileCheck %s < %t --check-prefix=MISSING-FP16
+
+[0x02,0x08,0x21,0xfc]
+# CHECK-FP16: vcmla.f16       d0, d1, d2, #0
+# MISSING-FP16: warning: invalid instruction encoding
+[0x44,0x08,0x22,0xfc]
+# CHECK-FP16: vcmla.f16       q0, q1, q2, #0
+# MISSING-FP16: warning: invalid instruction encoding
+[0x02,0x08,0x31,0xfc]
+# CHECK: vcmla.f32       d0, d1, d2, #0
+# MISSING: warning: invalid instruction encoding
+[0x44,0x08,0x32,0xfc]
+# CHECK: vcmla.f32       q0, q1, q2, #0
+# MISSING: warning: invalid instruction encoding
+[0x02,0x08,0xb1,0xfc]
+# CHECK: vcmla.f32       d0, d1, d2, #90
+# MISSING: warning: invalid instruction encoding
+[0x02,0x08,0x31,0xfd]
+# CHECK: vcmla.f32       d0, d1, d2, #180
+# MISSING: warning: invalid instruction encoding
+[0x02,0x08,0xb1,0xfd]
+# CHECK: vcmla.f32       d0, d1, d2, #270
+# MISSING: warning: invalid instruction encoding
+[0x02,0x08,0x81,0xfc]
+# CHECK-FP16: vcadd.f16       d0, d1, d2, #90
+# MISSING-FP16: warning: invalid instruction encoding
+[0x44,0x08,0x82,0xfc]
+# CHECK-FP16: vcadd.f16       q0, q1, q2, #90
+# MISSING-FP16: warning: invalid instruction encoding
+[0x02,0x08,0x91,0xfc]
+# CHECK: vcadd.f32       d0, d1, d2, #90
+# MISSING: warning: invalid instruction encoding
+[0x44,0x08,0x92,0xfc]
+# CHECK: vcadd.f32       q0, q1, q2, #90
+# MISSING: warning: invalid instruction encoding
+[0x02,0x08,0x91,0xfd]
+# CHECK: vcadd.f32       d0, d1, d2, #270
+# MISSING: warning: invalid instruction encoding
+[0x02,0x08,0x01,0xfe]
+# CHECK-FP16: vcmla.f16       d0, d1, d2[0], #0
+# MISSING-FP16: warning: invalid instruction encoding
+[0x42,0x08,0x02,0xfe]
+# CHECK-FP16: vcmla.f16       q0, q1, d2[0], #0
+# MISSING-FP16: warning: invalid instruction encoding
+[0x02,0x08,0x81,0xfe]
+# CHECK: vcmla.f32       d0, d1, d2[0], #0
+# MISSING: warning: invalid instruction encoding
+[0x42,0x08,0x82,0xfe]
+# CHECK: vcmla.f32       q0, q1, d2[0], #0
+# MISSING: warning: invalid instruction encoding
+[0x02,0x08,0x91,0xfe]
+# CHECK: vcmla.f32       d0, d1, d2[0], #90
+# MISSING: warning: invalid instruction encoding
+[0x02,0x08,0xa1,0xfe]
+# CHECK: vcmla.f32       d0, d1, d2[0], #180
+# MISSING: warning: invalid instruction encoding
+[0x02,0x08,0xb1,0xfe]
+# CHECK: vcmla.f32       d0, d1, d2[0], #270
+# MISSING: warning: invalid instruction encoding
+[0x22,0x08,0x01,0xfe]
+# CHECK-FP16: vcmla.f16       d0, d1, d2[1], #0
+# MISSING-FP16: warning: invalid instruction encoding

test/MC/Disassembler/ARM/neon-complex-thumb.txt

+# RUN:     llvm-mc -triple thumbv8a -mattr=+v8.3a,+neon,+fullfp16 -disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP16
+# RUN: not llvm-mc -triple thumbv8a -mattr=+v8.2a,+neon,+fullfp16 -disassemble < %s 2>&1 | FileCheck %s --check-prefix=MISSING --check-prefix=MISSING-FP16
+# RUN: not llvm-mc -triple thumbv8a -mattr=+v8.3a,-neon,+fullfp16 -disassemble < %s 2>&1 | FileCheck %s --check-prefix=MISSING --check-prefix=MISSING-FP16
+# RUN: not llvm-mc -triple thumbv8a -mattr=+v8.3a,+neon,-fullfp16 -disassemble < %s 2>%t | FileCheck %s --check-prefix=CHECK
+# RUN: FileCheck %s < %t --check-prefix=MISSING-FP16
+
+[0x21,0xfc,0x02,0x08]
+# CHECK-FP16: vcmla.f16       d0, d1, d2, #0
+# MISSING-FP16: warning: invalid instruction encoding
+[0x22,0xfc,0x44,0x08]
+# CHECK-FP16: vcmla.f16       q0, q1, q2, #0
+# MISSING-FP16: warning: invalid instruction encoding
+[0x31,0xfc,0x02,0x08]
+# CHECK: vcmla.f32       d0, d1, d2, #0
+# MISSING: warning: invalid instruction encoding
+[0x32,0xfc,0x44,0x08]
+# CHECK: vcmla.f32       q0, q1, q2, #0
+# MISSING: warning: invalid instruction encoding
+[0xb1,0xfc,0x02,0x08]
+# CHECK: vcmla.f32       d0, d1, d2, #90
+# MISSING: warning: invalid instruction encoding
+[0x31,0xfd,0x02,0x08]
+# CHECK: vcmla.f32       d0, d1, d2, #180
+# MISSING: warning: invalid instruction encoding
+[0xb1,0xfd,0x02,0x08]
+# CHECK: vcmla.f32       d0, d1, d2, #270
+# MISSING: warning: invalid instruction encoding
+[0x81,0xfc,0x02,0x08]
+# CHECK-FP16: vcadd.f16       d0, d1, d2, #90
+# MISSING-FP16: warning: invalid instruction encoding
+[0x82,0xfc,0x44,0x08]
+# CHECK-FP16: vcadd.f16       q0, q1, q2, #90
+# MISSING-FP16: warning: invalid instruction encoding
+[0x91,0xfc,0x02,0x08]
+# CHECK: vcadd.f32       d0, d1, d2, #90
+# MISSING: warning: invalid instruction encoding
+[0x92,0xfc,0x44,0x08]
+# CHECK: vcadd.f32       q0, q1, q2, #90
+# MISSING: warning: invalid instruction encoding
+[0x91,0xfd,0x02,0x08]
+# CHECK: vcadd.f32       d0, d1, d2, #270
+# MISSING: warning: invalid instruction encoding
+[0x01,0xfe,0x02,0x08]
+# CHECK-FP16: vcmla.f16       d0, d1, d2[0], #0
+# MISSING-FP16: warning: invalid instruction encoding
+[0x02,0xfe,0x42,0x08]
+# CHECK-FP16: vcmla.f16       q0, q1, d2[0], #0
+# MISSING-FP16: warning: invalid instruction encoding
+[0x81,0xfe,0x02,0x08]
+# CHECK: vcmla.f32       d0, d1, d2[0], #0
+# MISSING: warning: invalid instruction encoding
+[0x82,0xfe,0x42,0x08]
+# CHECK: vcmla.f32       q0, q1, d2[0], #0
+# MISSING: warning: invalid instruction encoding
+[0x91,0xfe,0x02,0x08]
+# CHECK: vcmla.f32       d0, d1, d2[0], #90
+# MISSING: warning: invalid instruction encoding
+[0xa1,0xfe,0x02,0x08]
+# CHECK: vcmla.f32       d0, d1, d2[0], #180
+# MISSING: warning: invalid instruction encoding
+[0xb1,0xfe,0x02,0x08]
+# CHECK: vcmla.f32       d0, d1, d2[0], #270
+# MISSING: warning: invalid instruction encoding
+[0x01,0xfe,0x22,0x08]
+# CHECK-FP16: vcmla.f16       d0, d1, d2[1], #0
+# MISSING-FP16: warning: invalid instruction encoding