[PowerPC][Altivec] Add vnot extended mnemonic

[brunoalr]

Summary

vnot vX,vY is an alias to vnor X,vY,VY

[hfinkel]

This should also have a test in test/MC/PowerPC/ppc64-encoding-vmx.s near the other vnor tests. Otherwise, this LGTM.

[brunoalr]

• Merge branch 'master' into vnot
• Add tests

[brunoalr]

In D29225#658873, @hfinkel wrote:

This should also have a test in test/MC/PowerPC/ppc64-encoding-vmx.s near the other vnor tests. Otherwise, this LGTM.

Test added :)

lib/Target/PowerPC/PPCInstrAltivec.td

 }
 }
 } // VALU Operations.
 
 //===----------------------------------------------------------------------===//
 // Additional Altivec Patterns
 //
 
+// Extended mnemonics
+def : InstAlias<"vnot $vD, $vA", (VNOR vrrc:$vD, vrrc:$vA, vrrc:$vA)>;
+
 // Loads.
 def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;
 
 // Stores.
 def : Pat<(store v4i32:$rS, xoaddr:$dst),
           (STVX $rS, xoaddr:$dst)>;
 
 // Bit conversions.

test/CodeGen/PowerPC/vec_cmp.ll

 define <16 x i8> @v16si8_cmp_ne(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
 entry:
   %cmp = icmp ne <16 x i8> %x, %y
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
 ; CHECK-LABEL:     v16si8_cmp_ne:
 ; CHECK:     vcmpequb [[RET:[0-9]+]], 2, 3
-; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
+; CHECK-NEXT: vnot     2, [[RET]]
 
 define <16 x i8> @v16si8_cmp_le(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
 entry:
   %cmp = icmp sle <16 x i8> %x, %y
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
 ; CHECK-LABEL:      v16si8_cmp_le:
 ; CHECK:      vcmpgtsb [[RET:[0-9]+]], 2, 3
-; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
+; CHECK-NEXT: vnot     2, [[RET]]
 
 define <16 x i8> @v16ui8_cmp_le(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
 entry:
   %cmp = icmp ule <16 x i8> %x, %y
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
 ; CHECK-LABEL:      v16ui8_cmp_le:
 ; CHECK:      vcmpgtub [[RET:[0-9]+]], 2, 3
-; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
+; CHECK-NEXT: vnot     2, [[RET]]
 
 define <16 x i8> @v16si8_cmp_lt(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
 entry:
   %cmp = icmp slt <16 x i8> %x, %y
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
 ; CHECK-LABEL: v16si8_cmp_lt:

 define <16 x i8> @v16si8_cmp_ge(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
 entry:
   %cmp = icmp sge <16 x i8> %x, %y
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
 ; CHECK-LABEL:      v16si8_cmp_ge:
 ; CHECK:      vcmpgtsb [[RET:[0-9]+]], 3, 2
-; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
+; CHECK-NEXT: vnot     2, [[RET]]
 
 define <16 x i8> @v16ui8_cmp_ge(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
 entry:
   %cmp = icmp uge <16 x i8> %x, %y
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
 ; CHECK-LABEL:      v16ui8_cmp_ge:
 ; CHECK:      vcmpgtub [[RET:[0-9]+]], 3, 2
-; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
+; CHECK-NEXT: vnot     2, [[RET]]
 
 
 define <32 x i8> @v32si8_cmp(<32 x i8> %x, <32 x i8> %y) nounwind readnone {
   %cmp = icmp eq <32 x i8> %x, %y
   %sext = sext <32 x i1> %cmp to <32 x i8>
   ret <32 x i8> %sext
 }
 ; CHECK-LABEL: v32si8_cmp:

 define <8 x i16> @v8si16_cmp_ne(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
 entry:
   %cmp = icmp ne <8 x i16> %x, %y
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
 ; CHECK-LABEL:      v8si16_cmp_ne:
 ; CHECK:      vcmpequh [[RET:[0-9]+]], 2, 3
-; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
+; CHECK-NEXT: vnot     2, [[RET]]
 
 define <8 x i16> @v8si16_cmp_le(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
 entry:
   %cmp = icmp sle <8 x i16> %x, %y
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
 ; CHECK-LABEL:      v8si16_cmp_le:
 ; CHECK:      vcmpgtsh [[RET:[0-9]+]], 2, 3
-; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
+; CHECK-NEXT: vnot     2, [[RET]]
 
 define <8 x i16> @v8ui16_cmp_le(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
 entry:
   %cmp = icmp ule <8 x i16> %x, %y
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
 ; CHECK-LABEL:      v8ui16_cmp_le:
 ; CHECK:      vcmpgtuh [[RET:[0-9]+]], 2, 3
-; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
+; CHECK-NEXT: vnot     2, [[RET]]
 
 define <8 x i16> @v8si16_cmp_lt(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
 entry:
   %cmp = icmp slt <8 x i16> %x, %y
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
 ; CHECK-LABEL: v8si16_cmp_lt:

 define <8 x i16> @v8si16_cmp_ge(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
 entry:
   %cmp = icmp sge <8 x i16> %x, %y
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
 ; CHECK-LABEL:      v8si16_cmp_ge:
 ; CHECK:      vcmpgtsh [[RET:[0-9]+]], 3, 2
-; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
+; CHECK-NEXT: vnot     2, [[RET]]
 
 define <8 x i16> @v8ui16_cmp_ge(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
 entry:
   %cmp = icmp uge <8 x i16> %x, %y
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
 ; CHECK-LABEL:      v8ui16_cmp_ge:
 ; CHECK:      vcmpgtuh [[RET:[0-9]+]], 3, 2
-; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
+; CHECK-NEXT: vnot     2, [[RET]]
 
 
 define <16 x i16> @v16si16_cmp(<16 x i16> %x, <16 x i16> %y) nounwind readnone {
   %cmp = icmp eq <16 x i16> %x, %y
   %sext = sext <16 x i1> %cmp to <16 x i16>
   ret <16 x i16> %sext
 }
 ; CHECK-LABEL: v16si16_cmp:

 define <4 x i32> @v4si32_cmp_ne(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
 entry:
   %cmp = icmp ne <4 x i32> %x, %y
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
 ; CHECK-LABEL:      v4si32_cmp_ne:
 ; CHECK:      vcmpequw [[RCMP:[0-9]+]], 2, 3
-; CHECK-NEXT: vnor     2, [[RCMP]], [[RCMP]]
+; CHECK-NEXT: vnot     2, [[RCMP]]
 
 define <4 x i32> @v4si32_cmp_le(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
 entry:
   %cmp = icmp sle <4 x i32> %x, %y
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
 ; CHECK-LABEL:      v4si32_cmp_le:
 ; CHECK:      vcmpgtsw [[RET:[0-9]+]], 2, 3
-; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
+; CHECK-NEXT: vnot     2, [[RET]]
 
 define <4 x i32> @v4ui32_cmp_le(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
 entry:
   %cmp = icmp ule <4 x i32> %x, %y
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
 ; CHECK-LABEL:      v4ui32_cmp_le:
 ; CHECK:      vcmpgtuw [[RET:[0-9]+]], 2, 3
-; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
+; CHECK-NEXT: vnot     2, [[RET]]
 
 define <4 x i32> @v4si32_cmp_lt(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
 entry:
   %cmp = icmp slt <4 x i32> %x, %y
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
 ; CHECK-LABEL: v4si32_cmp_lt:

 define <4 x i32> @v4si32_cmp_ge(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
 entry:
   %cmp = icmp sge <4 x i32> %x, %y
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
 ; CHECK-LABEL:      v4si32_cmp_ge:
 ; CHECK:      vcmpgtsw [[RET:[0-9]+]], 3, 2
-; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
+; CHECK-NEXT: vnot     2, [[RET]]
 
 define <4 x i32> @v4ui32_cmp_ge(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
 entry:
   %cmp = icmp uge <4 x i32> %x, %y
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
 ; CHECK-LABEL:      v4ui32_cmp_ge:
 ; CHECK:      vcmpgtuw [[RET:[0-9]+]], 3, 2
-; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
+; CHECK-NEXT: vnot     2, [[RET]]
 
 
 define <8 x i32> @v8si32_cmp(<8 x i32> %x, <8 x i32> %y) nounwind readnone {
   %cmp = icmp eq <8 x i32> %x, %y
   %sext = sext <8 x i1> %cmp to <8 x i32>
   ret <8 x i32> %sext
 }
 ; CHECK-LABEL: v8si32_cmp:

 entry:
   %cmp = fcmp une <4 x float> %x, %y
   %sext = sext <4 x i1> %cmp to <4 x i32>
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }
 ; CHECK-LABEL:      v4f32_cmp_ne:
 ; CHECK:      vcmpeqfp [[RET:[0-9]+]], 2, 3
-; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
+; CHECK-NEXT: vnot     2, [[RET]]
 
 define <4 x float> @v4f32_cmp_le(<4 x float> %x, <4 x float> %y) nounwind readnone {
 entry:
   %cmp = fcmp ole <4 x float> %x, %y
   %sext = sext <4 x i1> %cmp to <4 x i32>
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }

 entry:
   %cmp = fcmp ule <4 x float> %x, %y
   %sext = sext <4 x i1> %cmp to <4 x i32>
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }
 ; CHECK-LABEL: v4f32_cmp_ule:
 ; CHECK:      vcmpgtfp [[RET:[0-9]+]], 2, 3
-; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
+; CHECK-NEXT: vnot     2, [[RET]]
 
 define <4 x float> @v4f32_cmp_ult(<4 x float> %x, <4 x float> %y) nounwind readnone {
 entry:
   %cmp = fcmp ult <4 x float> %x, %y
   %sext = sext <4 x i1> %cmp to <4 x i32>
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }
 ; CHECK-LABEL: v4f32_cmp_ult:
 ; CHECK:      vcmpgefp [[RET:[0-9]+]], 2, 3
-; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
+; CHECK-NEXT: vnot     2, [[RET]]
 
 define <4 x float> @v4f32_cmp_uge(<4 x float> %x, <4 x float> %y) nounwind readnone {
 entry:
   %cmp = fcmp uge <4 x float> %x, %y
   %sext = sext <4 x i1> %cmp to <4 x i32>
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }
 ; CHECK-LABEL: v4f32_cmp_uge:
 ; CHECK:      vcmpgtfp [[RET:[0-9]+]], 3, 2
-; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
+; CHECK-NEXT: vnot     2, [[RET]]
 
 define <4 x float> @v4f32_cmp_ugt(<4 x float> %x, <4 x float> %y) nounwind readnone {
 entry:
   %cmp = fcmp ugt <4 x float> %x, %y
   %sext = sext <4 x i1> %cmp to <4 x i32>
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }
 ; CHECK-LABEL: v4f32_cmp_ugt:
 ; CHECK:      vcmpgefp [[RET:[0-9]+]], 3, 2
-; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
+; CHECK-NEXT: vnot     2, [[RET]]
 
 
 define <8 x float> @v8f32_cmp(<8 x float> %x, <8 x float> %y) nounwind readnone {
 entry:
   %cmp = fcmp oeq <8 x float> %x, %y
   %sext = sext <8 x i1> %cmp to <8 x i32>
   %0 = bitcast <8 x i32> %sext to <8 x float>
   ret <8 x float> %0
 }
 ; CHECK-LABEL: v8f32_cmp:
 ; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}