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Differential D29218

[mips][ias] Further relax operands of certain assembly instructions
ClosedPublic

Authored by sdardis on Jan 27 2017, 3:07 AM.

Details

Reviewers
slthakur
seanbruno
Commits
rGd410fc8f280f: [mips][ias] Further relax operands of certain assembly instructions
rL295965: [mips][ias] Further relax operands of certain assembly instructions
Summary

This patch adjusts the most relaxed predicate of immediate operands to accept
immediate forms such as ~(0xf0000000|0x000f00000). Previously these forms
would be accepted by GAS and rejected by IAS.

This partially resolves PR/30383.

Thanks to Sean Bruno for reporting the issue!

Diff Detail

Repository
rL LLVM

Event Timeline

sdardis created this revision.Jan 27 2017, 3:07 AM
seanbruno accepted this revision.Jan 31 2017, 2:36 PM

Yep, this works for me on FreeBSD's kernel.

This revision is now accepted and ready to land.Jan 31 2017, 2:37 PM
seanbruno added a comment.Feb 22 2017, 2:20 PM

This looks good from here. I think it can be committed.

Closed by commit rL295965: [mips][ias] Further relax operands of certain assembly instructions (authored by sdardis). · Explain WhyFeb 23 2017, 4:52 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
AsmParser/
51 lines
33 lines
80 lines
test/
MC/
Mips/
78 lines

Diff 89499

llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Show First 20 Lines • Show All 2,373 Lines • ▼ Show 20 Lines case Mips::Ulhu:
return expandUlh(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success; return expandUlh(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::Ush: case Mips::Ush:
return expandUsh(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; return expandUsh(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::Ulw: case Mips::Ulw:
case Mips::Usw: case Mips::Usw:
return expandUxw(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; return expandUxw(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::NORImm: case Mips::NORImm:
return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::ADDi: case Mips::ADDi: case Mips::ADDi_MM:
case Mips::ADDiu: case Mips::ADDiu: case Mips::ADDiu_MM:
case Mips::SLTi: case Mips::SLTi: case Mips::SLTi_MM:
case Mips::SLTiu: case Mips::SLTiu: case Mips::SLTiu_MM:
if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() && if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() &&
Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) { Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) {
int64_t ImmValue = Inst.getOperand(2).getImm(); int64_t ImmValue = Inst.getOperand(2).getImm();
if (isInt<16>(ImmValue)) if (isInt<16>(ImmValue))
return MER_NotAMacro; return MER_NotAMacro;
return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail
: MER_Success; : MER_Success;
} }
return MER_NotAMacro; return MER_NotAMacro;
case Mips::ANDi: case Mips::ANDi: case Mips::ANDi_MM:
case Mips::ORi: case Mips::ORi: case Mips::ORi_MM:
case Mips::XORi: case Mips::XORi: case Mips::XORi_MM:
if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() && if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() &&
Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) { Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) {
int64_t ImmValue = Inst.getOperand(2).getImm(); int64_t ImmValue = Inst.getOperand(2).getImm();
if (isUInt<16>(ImmValue)) if (isUInt<16>(ImmValue))
return MER_NotAMacro; return MER_NotAMacro;
return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail
: MER_Success; : MER_Success;
} }
▲ Show 20 Lines • Show All 1,410 Lines • ▼ Show 20 Lines if (DstReg == SrcReg) {
FinalDstReg = DstReg; FinalDstReg = DstReg;
DstReg = ATReg; DstReg = ATReg;
} }
if (!loadImmediate(ImmValue, DstReg, Mips::NoRegister, Is32Bit, false, Inst.getLoc(), Out, STI)) { if (!loadImmediate(ImmValue, DstReg, Mips::NoRegister, Is32Bit, false, Inst.getLoc(), Out, STI)) {
switch (FinalOpcode) { switch (FinalOpcode) {
default: default:
llvm_unreachable("unimplemented expansion"); llvm_unreachable("unimplemented expansion");
case (Mips::ADDi): case Mips::ADDi:
FinalOpcode = Mips::ADD; FinalOpcode = Mips::ADD;
break; break;
case (Mips::ADDiu): case Mips::ADDiu:
FinalOpcode = Mips::ADDu; FinalOpcode = Mips::ADDu;
break; break;
case (Mips::ANDi): case Mips::ANDi:
FinalOpcode = Mips::AND; FinalOpcode = Mips::AND;
break; break;
case (Mips::NORImm): case Mips::NORImm:
FinalOpcode = Mips::NOR; FinalOpcode = Mips::NOR;
break; break;
case (Mips::ORi): case Mips::ORi:
FinalOpcode = Mips::OR; FinalOpcode = Mips::OR;
break; break;
case (Mips::SLTi): case Mips::SLTi:
FinalOpcode = Mips::SLT; FinalOpcode = Mips::SLT;
break; break;
case (Mips::SLTiu): case Mips::SLTiu:
FinalOpcode = Mips::SLTu; FinalOpcode = Mips::SLTu;
break; break;
case (Mips::XORi): case Mips::XORi:
FinalOpcode = Mips::XOR; FinalOpcode = Mips::XOR;
break; break;
case Mips::ADDi_MM:
FinalOpcode = Mips::ADD_MM;
break;
case Mips::ADDiu_MM:
FinalOpcode = Mips::ADDu_MM;
break;
case Mips::ANDi_MM:
FinalOpcode = Mips::AND_MM;
break;
case Mips::ORi_MM:
FinalOpcode = Mips::OR_MM;
break;
case Mips::SLTi_MM:
FinalOpcode = Mips::SLT_MM;
break;
case Mips::SLTiu_MM:
FinalOpcode = Mips::SLTu_MM;
break;
case Mips::XORi_MM:
FinalOpcode = Mips::XOR_MM;
break;
} }
if (FinalDstReg == Mips::NoRegister) if (FinalDstReg == Mips::NoRegister)
TOut.emitRRR(FinalOpcode, DstReg, DstReg, SrcReg, IDLoc, STI); TOut.emitRRR(FinalOpcode, DstReg, DstReg, SrcReg, IDLoc, STI);
else else
TOut.emitRRR(FinalOpcode, FinalDstReg, FinalDstReg, DstReg, IDLoc, STI); TOut.emitRRR(FinalOpcode, FinalDstReg, FinalDstReg, DstReg, IDLoc, STI);
return false; return false;
} }
▲ Show 20 Lines • Show All 3,333 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td

Show First 20 Lines • Show All 1,130 Lines • ▼ Show 20 Lines def : MipsInstAlias<
"sgt $rs, $rt", "sgt $rs, $rt",
(SLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; (SLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias< def : MipsInstAlias<
"sgtu $rd, $rs, $rt", "sgtu $rd, $rs, $rt",
(SLTu_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; (SLTu_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias< def : MipsInstAlias<
"sgtu $rs, $rt", "sgtu $rs, $rt",
(SLTu_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; (SLTu_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"slt $rs, $rt, $imm",
(SLTi_MM GPR32Opnd:$rs, GPR32Opnd:$rt,
simm32_relaxed:$imm), 0>;
def : MipsInstAlias<"sltu $rs, $rt, $imm",
(SLTiu_MM GPR32Opnd:$rs, GPR32Opnd:$rt,
simm32_relaxed:$imm), 0>;
def : MipsInstAlias<"sll $rd, $rt, $rs", def : MipsInstAlias<"sll $rd, $rt, $rs",
(SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"sra $rd, $rt, $rs", def : MipsInstAlias<"sra $rd, $rt, $rs",
(SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"srl $rd, $rt, $rs", def : MipsInstAlias<"srl $rd, $rt, $rs",
(SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"sll $rd, $rt", def : MipsInstAlias<"sll $rd, $rt",
(SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>; (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
def : MipsInstAlias<"sra $rd, $rt", def : MipsInstAlias<"sra $rd, $rt",
(SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>; (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
def : MipsInstAlias<"srl $rd, $rt", def : MipsInstAlias<"srl $rd, $rt",
(SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>; (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
def : MipsInstAlias<"sll $rd, $shamt", def : MipsInstAlias<"sll $rd, $shamt",
(SLL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; (SLL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
def : MipsInstAlias<"sra $rd, $shamt", def : MipsInstAlias<"sra $rd, $shamt",
(SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; (SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
def : MipsInstAlias<"srl $rd, $shamt", def : MipsInstAlias<"srl $rd, $shamt",
(SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
def : MipsInstAlias<"rotr $rt, $imm", def : MipsInstAlias<"rotr $rt, $imm",
(ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>; (ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>;
def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>; def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>;
def : MipsInstAlias<"and $rs, $rt, $imm",
(ANDi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi_MM>;
def : MipsInstAlias<"and $rs, $imm",
(ANDi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>; defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu_MM>;
def : MipsInstAlias<"or $rs, $rt, $imm",
(ORi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi_MM>;
def : MipsInstAlias<"or $rs, $imm",
(ORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>; defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi_MM>;
def : MipsInstAlias<"xor $rs, $rt, $imm",
(XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi_MM>;
def : MipsInstAlias<"xor $rs, $imm",
(XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>; defm : OneOrTwoOperandMacroImmediateAlias<"slt", SLTi_MM>;
defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu_MM>;
def : MipsInstAlias<"not $rt, $rs", def : MipsInstAlias<"not $rt, $rs",
(NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
def : MipsInstAlias<"not $rt", def : MipsInstAlias<"not $rt",
(NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>; (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>;
def : MipsInstAlias<"bnez $rs,$offset", def : MipsInstAlias<"bnez $rs,$offset",
(BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; (BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
def : MipsInstAlias<"beqz $rs,$offset", def : MipsInstAlias<"beqz $rs,$offset",
(BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; (BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
def : MipsInstAlias<"seh $rd", (SEH_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, def : MipsInstAlias<"seh $rd", (SEH_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
ISA_MIPS32R2_NOT_32R6_64R6; ISA_MIPS32R2_NOT_32R6_64R6;
def : MipsInstAlias<"seb $rd", (SEB_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, def : MipsInstAlias<"seb $rd", (SEB_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
ISA_MIPS32R2_NOT_32R6_64R6; ISA_MIPS32R2_NOT_32R6_64R6;
} }

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Show First 20 Lines • Show All 535 Lines • ▼ Show 20 Lines
def UImm32CoercedAsmOperandClass : UImmAnyAsmOperandClass<33, []> { def UImm32CoercedAsmOperandClass : UImmAnyAsmOperandClass<33, []> {
let Name = "UImm32_Coerced"; let Name = "UImm32_Coerced";
let DiagnosticType = "UImm32_Coerced"; let DiagnosticType = "UImm32_Coerced";
} }
def SImm32RelaxedAsmOperandClass def SImm32RelaxedAsmOperandClass
: SImmAsmOperandClass<32, [UImm32CoercedAsmOperandClass]> { : SImmAsmOperandClass<32, [UImm32CoercedAsmOperandClass]> {
let Name = "SImm32_Relaxed"; let Name = "SImm32_Relaxed";
let PredicateMethod = "isAnyImm<32>"; let PredicateMethod = "isAnyImm<33>";
let DiagnosticType = "SImm32_Relaxed"; let DiagnosticType = "SImm32_Relaxed";
} }
def SImm32AsmOperandClass def SImm32AsmOperandClass
: SImmAsmOperandClass<32, [SImm32RelaxedAsmOperandClass]>; : SImmAsmOperandClass<32, [SImm32RelaxedAsmOperandClass]>;
def ConstantUImm26AsmOperandClass def ConstantUImm26AsmOperandClass
: ConstantUImmAsmOperandClass<26, [SImm32AsmOperandClass]>; : ConstantUImmAsmOperandClass<26, [SImm32AsmOperandClass]>;
def ConstantUImm20AsmOperandClass def ConstantUImm20AsmOperandClass
: ConstantUImmAsmOperandClass<20, [ConstantUImm26AsmOperandClass]>; : ConstantUImmAsmOperandClass<20, [ConstantUImm26AsmOperandClass]>;
▲ Show 20 Lines • Show All 1,762 Lines • ▼ Show 20 Lines
def MULOUMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs, def MULOUMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs,
GPR32Opnd:$rt), GPR32Opnd:$rt),
"mulou\t$rd, $rs, $rt">, "mulou\t$rd, $rs, $rt">,
ISA_MIPS1_NOT_32R6_64R6; ISA_MIPS1_NOT_32R6_64R6;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instruction aliases // Instruction aliases
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
multiclass OneOrTwoOperandMacroImmediateAlias<string Memnomic,
Instruction Opcode> {
def : MipsInstAlias<!strconcat(Memnomic, " $rs, $rt, $imm"),
(Opcode GPR32Opnd:$rs,
GPR32Opnd:$rt,
simm32_relaxed:$imm), 0>;
def : MipsInstAlias<!strconcat(Memnomic, " $rs, $imm"),
(Opcode GPR32Opnd:$rs,
GPR32Opnd:$rs,
simm32_relaxed:$imm), 0>;
}
def : MipsInstAlias<"move $dst, $src", def : MipsInstAlias<"move $dst, $src",
(OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>, (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
GPR_32 { GPR_32 {
let AdditionalPredicates = [NotInMicroMips]; let AdditionalPredicates = [NotInMicroMips];
} }
def : MipsInstAlias<"move $dst, $src", def : MipsInstAlias<"move $dst, $src",
(ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>, (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
GPR_32 { GPR_32 {
let AdditionalPredicates = [NotInMicroMips]; let AdditionalPredicates = [NotInMicroMips];
} }
def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>, def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
ISA_MIPS1_NOT_32R6_64R6; ISA_MIPS1_NOT_32R6_64R6;
def : MipsInstAlias<
"addu $rs, $rt, $imm",
(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
def : MipsInstAlias<
"addu $rs, $imm",
(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
def : MipsInstAlias<
"add $rs, $rt, $imm",
(ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>,
ISA_MIPS1_NOT_32R6_64R6;
def : MipsInstAlias<
"add $rs, $imm",
(ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>,
ISA_MIPS1_NOT_32R6_64R6;
def : MipsInstAlias<
"and $rs, $rt, $imm",
(ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
def : MipsInstAlias<
"and $rs, $imm",
(ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>; def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
let Predicates = [NotInMicroMips] in { let Predicates = [NotInMicroMips] in {
def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>; def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
} }
def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32; def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
def : MipsInstAlias<"neg $rt, $rs", def : MipsInstAlias<"neg $rt, $rs",
(SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
def : MipsInstAlias<"neg $rt", def : MipsInstAlias<"neg $rt",
Show All 11 Lines def : MipsInstAlias<
(SLT GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; (SLT GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias< def : MipsInstAlias<
"sgtu $rd, $rs, $rt", "sgtu $rd, $rs, $rt",
(SLTu GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; (SLTu GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias< def : MipsInstAlias<
"sgtu $$rs, $rt", "sgtu $$rs, $rt",
(SLTu GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; (SLTu GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias< def : MipsInstAlias<
"slt $rs, $rt, $imm",
(SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
def : MipsInstAlias<
"sltu $rt, $rs, $imm",
(SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
def : MipsInstAlias<
"and $rs, $rt, $imm",
(ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
def : MipsInstAlias<
"and $rs, $imm",
(ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
def : MipsInstAlias<
"xor $rs, $rt, $imm",
(XORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
def : MipsInstAlias<
"xor $rs, $imm",
(XORi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
def : MipsInstAlias<
"or $rs, $rt, $imm",
(ORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
def : MipsInstAlias<
"or $rs, $imm",
(ORi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
def : MipsInstAlias<
"not $rt, $rs", "not $rt, $rs",
(NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
def : MipsInstAlias< def : MipsInstAlias<
"not $rt", "not $rt",
(NOR GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>; (NOR GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>;
def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi>, ISA_MIPS1_NOT_32R6_64R6;
defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu>;
defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi>;
defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi>;
defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi>;
defm : OneOrTwoOperandMacroImmediateAlias<"slt", SLTi>;
defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu>;
} }
def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>; def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>;
def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>; def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, COP2Opnd:$rd, 0), 0>; def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, COP2Opnd:$rd, 0), 0>;
def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 COP2Opnd:$rd, GPR32Opnd:$rt, 0), 0>; def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 COP2Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>; def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
} }
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def LoadAddrImm32 : LoadAddressFromImm32<"la", i32imm, GPR32Opnd>; def LoadAddrImm32 : LoadAddressFromImm32<"la", i32imm, GPR32Opnd>;
def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs), def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
"jal\t$rd, $rs"> ; "jal\t$rd, $rs"> ;
def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs), def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs),
"jal\t$rs"> ; "jal\t$rs"> ;
def NORImm : MipsAsmPseudoInst< def NORImm : MipsAsmPseudoInst<
(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), (outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm),
"nor\t$rs, $rt, $imm"> ; "nor\t$rs, $rt, $imm">;
def : MipsInstAlias<"nor\t$rs, $imm", (NORImm GPR32Opnd:$rs, GPR32Opnd:$rs,
simm32_relaxed:$imm)>;
let hasDelaySlot = 1, isCTI = 1 in { let hasDelaySlot = 1, isCTI = 1 in {
def BneImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), def BneImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
(ins imm64:$imm64, brtarget:$offset), (ins imm64:$imm64, brtarget:$offset),
"bne\t$rt, $imm64, $offset">; "bne\t$rt, $imm64, $offset">;
def BeqImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), def BeqImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
(ins imm64:$imm64, brtarget:$offset), (ins imm64:$imm64, brtarget:$offset),
"beq\t$rt, $imm64, $offset">; "beq\t$rt, $imm64, $offset">;
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llvm/trunk/test/MC/Mips/instalias-imm-expanding.s

Show All 17 Lines# CHECK: addi $4, $4, 0 # encoding: [0x00,0x00,0x84,0x20]
add $4, 0xFFFF add $4, 0xFFFF
# CHECK: ori $1, $zero, 65535 # encoding: [0xff,0xff,0x01,0x34] # CHECK: ori $1, $zero, 65535 # encoding: [0xff,0xff,0x01,0x34]
# CHECK: add $4, $4, $1 # encoding: [0x20,0x20,0x81,0x00] # CHECK: add $4, $4, $1 # encoding: [0x20,0x20,0x81,0x00]
add $4, 0x10000 add $4, 0x10000
# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] # CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
# CHECK: add $4, $4, $1 # encoding: [0x20,0x20,0x81,0x00] # CHECK: add $4, $4, $1 # encoding: [0x20,0x20,0x81,0x00]
add $4, 0xFFFFFFFF add $4, 0xFFFFFFFF
# CHECK: addi $4, $4, -1 # encoding: [0xff,0xff,0x84,0x20] # CHECK: addi $4, $4, -1 # encoding: [0xff,0xff,0x84,0x20]
add $5, ~(0xf0000000|0x0f000000|0x000000f0)
# CHECK: lui $1, 255 # encoding: [0xff,0x00,0x01,0x3c]
# CHECK: ori $1, $1, 65295 # encoding: [0x0f,0xff,0x21,0x34]
# CHECK: add $5, $5, $1 # encoding: [0x20,0x28,0xa1,0x00]
add $4, $5, -0x80000000 add $4, $5, -0x80000000
# CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c] # CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c]
# CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00] # CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00]
add $4, $5, -0x8001 add $4, $5, -0x8001
# CHECK: lui $4, 65535 # encoding: [0xff,0xff,0x04,0x3c] # CHECK: lui $4, 65535 # encoding: [0xff,0xff,0x04,0x3c]
# CHECK: ori $4, $4, 32767 # encoding: [0xff,0x7f,0x84,0x34] # CHECK: ori $4, $4, 32767 # encoding: [0xff,0x7f,0x84,0x34]
# CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00] # CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00]
add $4, $5, -0x8000 add $4, $5, -0x8000
# CHECK: addi $4, $5, -32768 # encoding: [0x00,0x80,0xa4,0x20] # CHECK: addi $4, $5, -32768 # encoding: [0x00,0x80,0xa4,0x20]
add $4, $5, 0 add $4, $5, 0
# CHECK: addi $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x20] # CHECK: addi $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x20]
add $4, $5, 0xFFFF add $4, $5, 0xFFFF
# CHECK: ori $4, $zero, 65535 # encoding: [0xff,0xff,0x04,0x34] # CHECK: ori $4, $zero, 65535 # encoding: [0xff,0xff,0x04,0x34]
# CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00] # CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00]
add $4, $5, 0x10000 add $4, $5, 0x10000
# CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c] # CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c]
# CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00] # CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00]
add $4, $5, 0xFFFFFFFF add $4, $5, 0xFFFFFFFF
# CHECK: addi $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x20] # CHECK: addi $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x20]
add $4, $5, ~(0xf0000000|0x0f000000|0x000000f0)
# CHECK: lui $4, 255 # encoding: [0xff,0x00,0x04,0x3c]
# CHECK: ori $4, $4, 65295 # encoding: [0x0f,0xff,0x84,0x34]
# CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00]
addu $4, -0x80000000 addu $4, -0x80000000
# CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c] # CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c]
# CHECK: addu $4, $4, $1 # encoding: [0x21,0x20,0x81,0x00] # CHECK: addu $4, $4, $1 # encoding: [0x21,0x20,0x81,0x00]
addu $4, -0x8001 addu $4, -0x8001
# CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c] # CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c]
# CHECK: ori $1, $1, 32767 # encoding: [0xff,0x7f,0x21,0x34] # CHECK: ori $1, $1, 32767 # encoding: [0xff,0x7f,0x21,0x34]
# CHECK: addu $4, $4, $1 # encoding: [0x21,0x20,0x81,0x00] # CHECK: addu $4, $4, $1 # encoding: [0x21,0x20,0x81,0x00]
addu $4, -0x8000 addu $4, -0x8000
# CHECK: addiu $4, $4, -32768 # encoding: [0x00,0x80,0x84,0x24] # CHECK: addiu $4, $4, -32768 # encoding: [0x00,0x80,0x84,0x24]
addu $4, 0 addu $4, 0
# CHECK: addiu $4, $4, 0 # encoding: [0x00,0x00,0x84,0x24] # CHECK: addiu $4, $4, 0 # encoding: [0x00,0x00,0x84,0x24]
addu $4, 0xFFFF addu $4, 0xFFFF
# CHECK: ori $1, $zero, 65535 # encoding: [0xff,0xff,0x01,0x34] # CHECK: ori $1, $zero, 65535 # encoding: [0xff,0xff,0x01,0x34]
# CHECK: addu $4, $4, $1 # encoding: [0x21,0x20,0x81,0x00] # CHECK: addu $4, $4, $1 # encoding: [0x21,0x20,0x81,0x00]
addu $4, 0x10000 addu $4, 0x10000
# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] # CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
# CHECK: addu $4, $4, $1 # encoding: [0x21,0x20,0x81,0x00] # CHECK: addu $4, $4, $1 # encoding: [0x21,0x20,0x81,0x00]
addu $4, 0xFFFFFFFF addu $4, 0xFFFFFFFF
# CHECK: addiu $4, $4, -1 # encoding: [0xff,0xff,0x84,0x24] # CHECK: addiu $4, $4, -1 # encoding: [0xff,0xff,0x84,0x24]
addu $5, ~(0xf0000000|0x0f000000|0x000000f0)
# CHECK: lui $1, 255 # encoding: [0xff,0x00,0x01,0x3c]
# CHECK: ori $1, $1, 65295 # encoding: [0x0f,0xff,0x21,0x34]
# CHECK: addu $5, $5, $1 # encoding: [0x21,0x28,0xa1,0x00]
addu $4, $5, -0x80000000 addu $4, $5, -0x80000000
# CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c] # CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c]
# CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00] # CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00]
addu $4, $5, -0x8001 addu $4, $5, -0x8001
# CHECK: lui $4, 65535 # encoding: [0xff,0xff,0x04,0x3c] # CHECK: lui $4, 65535 # encoding: [0xff,0xff,0x04,0x3c]
# CHECK: ori $4, $4, 32767 # encoding: [0xff,0x7f,0x84,0x34] # CHECK: ori $4, $4, 32767 # encoding: [0xff,0x7f,0x84,0x34]
# CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00] # CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00]
addu $4, $5, -0x8000 addu $4, $5, -0x8000
# CHECK: addiu $4, $5, -32768 # encoding: [0x00,0x80,0xa4,0x24] # CHECK: addiu $4, $5, -32768 # encoding: [0x00,0x80,0xa4,0x24]
addu $4, $5, 0 addu $4, $5, 0
# CHECK: addiu $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x24] # CHECK: addiu $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x24]
addu $4, $5, 0xFFFF addu $4, $5, 0xFFFF
# CHECK: ori $4, $zero, 65535 # encoding: [0xff,0xff,0x04,0x34] # CHECK: ori $4, $zero, 65535 # encoding: [0xff,0xff,0x04,0x34]
# CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00] # CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00]
addu $4, $5, 0x10000 addu $4, $5, 0x10000
# CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c] # CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c]
# CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00] # CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00]
addu $4, $5, 0xFFFFFFFF addu $4, $5, 0xFFFFFFFF
# CHECK: addiu $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x24] # CHECK: addiu $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x24]
addu $4, $5, ~(0xf0000000|0x0f000000|0x000000f0)
# CHECK: lui $4, 255 # encoding: [0xff,0x00,0x04,0x3c]
# CHECK: ori $4, $4, 65295 # encoding: [0x0f,0xff,0x84,0x34]
# CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00]
and $4, -0x80000000 and $4, -0x80000000
# CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c] # CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c]
# CHECK: and $4, $4, $1 # encoding: [0x24,0x20,0x81,0x00] # CHECK: and $4, $4, $1 # encoding: [0x24,0x20,0x81,0x00]
and $4, -0x8001 and $4, -0x8001
# CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c] # CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c]
# CHECK: ori $1, $1, 32767 # encoding: [0xff,0x7f,0x21,0x34] # CHECK: ori $1, $1, 32767 # encoding: [0xff,0x7f,0x21,0x34]
# CHECK: and $4, $4, $1 # encoding: [0x24,0x20,0x81,0x00] # CHECK: and $4, $4, $1 # encoding: [0x24,0x20,0x81,0x00]
and $4, -0x8000 and $4, -0x8000
# CHECK: addiu $1, $zero, -32768 # encoding: [0x00,0x80,0x01,0x24] # CHECK: addiu $1, $zero, -32768 # encoding: [0x00,0x80,0x01,0x24]
and $4, 0 and $4, 0
# CHECK: andi $4, $4, 0 # encoding: [0x00,0x00,0x84,0x30] # CHECK: andi $4, $4, 0 # encoding: [0x00,0x00,0x84,0x30]
and $4, 0xFFFF and $4, 0xFFFF
# CHECK: andi $4, $4, 65535 # encoding: [0xff,0xff,0x84,0x30] # CHECK: andi $4, $4, 65535 # encoding: [0xff,0xff,0x84,0x30]
and $4, 0x10000 and $4, 0x10000
# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] # CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
# CHECK: and $4, $4, $1 # encoding: [0x24,0x20,0x81,0x00] # CHECK: and $4, $4, $1 # encoding: [0x24,0x20,0x81,0x00]
and $4, 0xFFFFFFFF and $4, 0xFFFFFFFF
# CHECK: addiu $1, $zero, -1 # encoding: [0xff,0xff,0x01,0x24] # CHECK: addiu $1, $zero, -1 # encoding: [0xff,0xff,0x01,0x24]
# CHECK: and $4, $4, $1 # encoding: [0x24,0x20,0x81,0x00] # CHECK: and $4, $4, $1 # encoding: [0x24,0x20,0x81,0x00]
and $5, ~(0xf0000000|0x0f000000|0x000000f0)
# CHECK: lui $1, 255 # encoding: [0xff,0x00,0x01,0x3c]
# CHECK: ori $1, $1, 65295 # encoding: [0x0f,0xff,0x21,0x34]
# CHECK: and $5, $5, $1 # encoding: [0x24,0x28,0xa1,0x00]
and $4, $5, -0x80000000 and $4, $5, -0x80000000
# CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c] # CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c]
# CHECK: and $4, $4, $5 # encoding: [0x24,0x20,0x85,0x00] # CHECK: and $4, $4, $5 # encoding: [0x24,0x20,0x85,0x00]
and $4, $5, -0x8001 and $4, $5, -0x8001
# CHECK: lui $4, 65535 # encoding: [0xff,0xff,0x04,0x3c] # CHECK: lui $4, 65535 # encoding: [0xff,0xff,0x04,0x3c]
# CHECK: ori $4, $4, 32767 # encoding: [0xff,0x7f,0x84,0x34] # CHECK: ori $4, $4, 32767 # encoding: [0xff,0x7f,0x84,0x34]
# CHECK: and $4, $4, $5 # encoding: [0x24,0x20,0x85,0x00] # CHECK: and $4, $4, $5 # encoding: [0x24,0x20,0x85,0x00]
and $4, $5, -0x8000 and $4, $5, -0x8000
# CHECK: addiu $4, $zero, -32768 # encoding: [0x00,0x80,0x04,0x24] # CHECK: addiu $4, $zero, -32768 # encoding: [0x00,0x80,0x04,0x24]
# CHECK: and $4, $4, $5 # encoding: [0x24,0x20,0x85,0x00] # CHECK: and $4, $4, $5 # encoding: [0x24,0x20,0x85,0x00]
and $4, $5, 0 and $4, $5, 0
# CHECK: andi $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x30] # CHECK: andi $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x30]
and $4, $5, 0xFFFF and $4, $5, 0xFFFF
# CHECK: andi $4, $5, 65535 # encoding: [0xff,0xff,0xa4,0x30] # CHECK: andi $4, $5, 65535 # encoding: [0xff,0xff,0xa4,0x30]
and $4, $5, 0x10000 and $4, $5, 0x10000
# CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c] # CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c]
# CHECK: and $4, $4, $5 # encoding: [0x24,0x20,0x85,0x00] # CHECK: and $4, $4, $5 # encoding: [0x24,0x20,0x85,0x00]
and $4, $5, 0xFFFFFFFF and $4, $5, 0xFFFFFFFF
# CHECK: addiu $4, $zero, -1 # encoding: [0xff,0xff,0x04,0x24] # CHECK: addiu $4, $zero, -1 # encoding: [0xff,0xff,0x04,0x24]
# CHECK: and $4, $4, $5 # encoding: [0x24,0x20,0x85,0x00] # CHECK: and $4, $4, $5 # encoding: [0x24,0x20,0x85,0x00]
and $4, $5, ~(0xf0000000|0x0f000000|0x000000f0)
# CHECK: lui $4, 255 # encoding: [0xff,0x00,0x04,0x3c]
# CHECK: ori $4, $4, 65295 # encoding: [0x0f,0xff,0x84,0x34]
# CHECK: and $4, $4, $5 # encoding: [0x24,0x20,0x85,0x00]
nor $4, $5, 0 nor $4, $5, 0
# CHECK: addiu $4, $zero, 0 # encoding: [0x00,0x00,0x04,0x24] # CHECK: addiu $4, $zero, 0 # encoding: [0x00,0x00,0x04,0x24]
# CHECK: nor $4, $4, $5 # encoding: [0x27,0x20,0x85,0x00] # CHECK: nor $4, $4, $5 # encoding: [0x27,0x20,0x85,0x00]
nor $4, $5, 1 nor $4, $5, 1
# CHECK: addiu $4, $zero, 1 # encoding: [0x01,0x00,0x04,0x24] # CHECK: addiu $4, $zero, 1 # encoding: [0x01,0x00,0x04,0x24]
# CHECK: nor $4, $4, $5 # encoding: [0x27,0x20,0x85,0x00] # CHECK: nor $4, $4, $5 # encoding: [0x27,0x20,0x85,0x00]
nor $4, $5, 0x8000 nor $4, $5, 0x8000
# CHECK: ori $4, $zero, 32768 # encoding: [0x00,0x80,0x04,0x34] # CHECK: ori $4, $zero, 32768 # encoding: [0x00,0x80,0x04,0x34]
# CHECK: nor $4, $4, $5 # encoding: [0x27,0x20,0x85,0x00] # CHECK: nor $4, $4, $5 # encoding: [0x27,0x20,0x85,0x00]
nor $4, $5, -0x8000 nor $4, $5, -0x8000
# CHECK: addiu $4, $zero, -32768 # encoding: [0x00,0x80,0x04,0x24] # CHECK: addiu $4, $zero, -32768 # encoding: [0x00,0x80,0x04,0x24]
# CHECK: nor $4, $4, $5 # encoding: [0x27,0x20,0x85,0x00] # CHECK: nor $4, $4, $5 # encoding: [0x27,0x20,0x85,0x00]
nor $4, $5, 0x10000 nor $4, $5, 0x10000
# CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c] # CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c]
# CHECK: nor $4, $4, $5 # encoding: [0x27,0x20,0x85,0x00] # CHECK: nor $4, $4, $5 # encoding: [0x27,0x20,0x85,0x00]
nor $4, $5, 0x1a5a5 nor $4, $5, 0x1a5a5
# CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c] # CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c]
# CHECK: ori $4, $4, 42405 # encoding: [0xa5,0xa5,0x84,0x34] # CHECK: ori $4, $4, 42405 # encoding: [0xa5,0xa5,0x84,0x34]
# CHECK: nor $4, $4, $5 # encoding: [0x27,0x20,0x85,0x00] # CHECK: nor $4, $4, $5 # encoding: [0x27,0x20,0x85,0x00]
nor $4, ~(0xf0000000|0x0f000000|0x000000f0)
# CHECK: lui $1, 255 # encoding: [0xff,0x00,0x01,0x3c]
# CHECK: ori $1, $1, 65295 # encoding: [0x0f,0xff,0x21,0x34]
# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00]
nor $4, 0
# CHECK: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24]
# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00]
nor $4, 1
# CHECK: addiu $1, $zero, 1 # encoding: [0x01,0x00,0x01,0x24]
# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00]
nor $4, 0x8000
# CHECK: ori $1, $zero, 32768 # encoding: [0x00,0x80,0x01,0x34]
# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00]
nor $4, -0x8000
# CHECK: addiu $1, $zero, -32768 # encoding: [0x00,0x80,0x01,0x24]
# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00]
nor $4, 0x10000
# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00]
nor $4, 0x1a5a5
# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
# CHECK: ori $1, $1, 42405 # encoding: [0xa5,0xa5,0x21,0x34]
# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00]
nor $4, ~(0xf0000000|0x0f000000|0x000000f0)
# CHECK: lui $1, 255 # encoding: [0xff,0x00,0x01,0x3c]
# CHECK: ori $1, $1, 65295 # encoding: [0x0f,0xff,0x21,0x34]
# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00]
or $4, -0x80000000 or $4, -0x80000000
# CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c] # CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c]
# CHECK: or $4, $4, $1 # encoding: [0x25,0x20,0x81,0x00] # CHECK: or $4, $4, $1 # encoding: [0x25,0x20,0x81,0x00]
or $4, -0x8001 or $4, -0x8001
# CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c] # CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c]
# CHECK: ori $1, $1, 32767 # encoding: [0xff,0x7f,0x21,0x34] # CHECK: ori $1, $1, 32767 # encoding: [0xff,0x7f,0x21,0x34]
# CHECK: or $4, $4, $1 # encoding: [0x25,0x20,0x81,0x00] # CHECK: or $4, $4, $1 # encoding: [0x25,0x20,0x81,0x00]
or $4, -0x8000 or $4, -0x8000
# CHECK: addiu $1, $zero, -32768 # encoding: [0x00,0x80,0x01,0x24] # CHECK: addiu $1, $zero, -32768 # encoding: [0x00,0x80,0x01,0x24]
# CHECK: or $4, $4, $1 # encoding: [0x25,0x20,0x81,0x00] # CHECK: or $4, $4, $1 # encoding: [0x25,0x20,0x81,0x00]
or $4, 0 or $4, 0
# CHECK: ori $4, $4, 0 # encoding: [0x00,0x00,0x84,0x34] # CHECK: ori $4, $4, 0 # encoding: [0x00,0x00,0x84,0x34]
or $4, 0xFFFF or $4, 0xFFFF
# CHECK: ori $4, $4, 65535 # encoding: [0xff,0xff,0x84,0x34] # CHECK: ori $4, $4, 65535 # encoding: [0xff,0xff,0x84,0x34]
or $4, 0x10000 or $4, 0x10000
# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] # CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
# CHECK: or $4, $4, $1 # encoding: [0x25,0x20,0x81,0x00] # CHECK: or $4, $4, $1 # encoding: [0x25,0x20,0x81,0x00]
or $4, 0xFFFFFFFF or $4, 0xFFFFFFFF
# CHECK: addiu $1, $zero, -1 # encoding: [0xff,0xff,0x01,0x24] # CHECK: addiu $1, $zero, -1 # encoding: [0xff,0xff,0x01,0x24]
# CHECK: or $4, $4, $1 # encoding: [0x25,0x20,0x81,0x00] # CHECK: or $4, $4, $1 # encoding: [0x25,0x20,0x81,0x00]
or $5, ~(0xf0000000|0x0f000000|0x000000f0)
# CHECK: lui $1, 255 # encoding: [0xff,0x00,0x01,0x3c]
# CHECK: ori $1, $1, 65295 # encoding: [0x0f,0xff,0x21,0x34]
# CHECK: or $5, $5, $1 # encoding: [0x25,0x28,0xa1,0x00]
or $4, $5, -0x80000000 or $4, $5, -0x80000000
# CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c] # CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c]
# CHECK: or $4, $4, $5 # encoding: [0x25,0x20,0x85,0x00] # CHECK: or $4, $4, $5 # encoding: [0x25,0x20,0x85,0x00]
or $4, $5, -0x8001 or $4, $5, -0x8001
# CHECK: lui $4, 65535 # encoding: [0xff,0xff,0x04,0x3c] # CHECK: lui $4, 65535 # encoding: [0xff,0xff,0x04,0x3c]
# CHECK: ori $4, $4, 32767 # encoding: [0xff,0x7f,0x84,0x34] # CHECK: ori $4, $4, 32767 # encoding: [0xff,0x7f,0x84,0x34]
# CHECK: or $4, $4, $5 # encoding: [0x25,0x20,0x85,0x00] # CHECK: or $4, $4, $5 # encoding: [0x25,0x20,0x85,0x00]
or $4, $5, -0x8000 or $4, $5, -0x8000
# CHECK: addiu $4, $zero, -32768 # encoding: [0x00,0x80,0x04,0x24] # CHECK: addiu $4, $zero, -32768 # encoding: [0x00,0x80,0x04,0x24]
# CHECK: or $4, $4, $5 # encoding: [0x25,0x20,0x85,0x00] # CHECK: or $4, $4, $5 # encoding: [0x25,0x20,0x85,0x00]
or $4, $5, 0 or $4, $5, 0
# CHECK: ori $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x34] # CHECK: ori $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x34]
or $4, $5, 0xFFFF or $4, $5, 0xFFFF
# CHECK: ori $4, $5, 65535 # encoding: [0xff,0xff,0xa4,0x34] # CHECK: ori $4, $5, 65535 # encoding: [0xff,0xff,0xa4,0x34]
or $4, $5, 0x10000 or $4, $5, 0x10000
# CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c] # CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c]
# CHECK: or $4, $4, $5 # encoding: [0x25,0x20,0x85,0x00] # CHECK: or $4, $4, $5 # encoding: [0x25,0x20,0x85,0x00]
or $4, $5, 0xFFFFFFFF or $4, $5, 0xFFFFFFFF
# CHECK: addiu $4, $zero, -1 # encoding: [0xff,0xff,0x04,0x24] # CHECK: addiu $4, $zero, -1 # encoding: [0xff,0xff,0x04,0x24]
# CHECK: or $4, $4, $5 # encoding: [0x25,0x20,0x85,0x00] # CHECK: or $4, $4, $5 # encoding: [0x25,0x20,0x85,0x00]
or $4, $5, ~(0xF0000000|0x0F000000|0x000000F0)
# CHECK: lui $4, 255 # encoding: [0xff,0x00,0x04,0x3c]
# CHECK: ori $4, $4, 65295 # encoding: [0x0f,0xff,0x84,0x34]
# CHECK: or $4, $4, $5 # encoding: [0x25,0x20,0x85,0x00]
slt $4, $5, -0x80000000 slt $4, $5, -0x80000000
# CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c] # CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c]
# CHECK: slt $4, $4, $5 # encoding: [0x2a,0x20,0x85,0x00] # CHECK: slt $4, $4, $5 # encoding: [0x2a,0x20,0x85,0x00]
slt $4, $5, -0x8001 slt $4, $5, -0x8001
# CHECK: lui $4, 65535 # encoding: [0xff,0xff,0x04,0x3c] # CHECK: lui $4, 65535 # encoding: [0xff,0xff,0x04,0x3c]
# CHECK: ori $4, $4, 32767 # encoding: [0xff,0x7f,0x84,0x34] # CHECK: ori $4, $4, 32767 # encoding: [0xff,0x7f,0x84,0x34]
# CHECK: slt $4, $4, $5 # encoding: [0x2a,0x20,0x85,0x00] # CHECK: slt $4, $4, $5 # encoding: [0x2a,0x20,0x85,0x00]
slt $4, $5, -0x8000 slt $4, $5, -0x8000
# CHECK: slti $4, $5, -32768 # encoding: [0x00,0x80,0xa4,0x28] # CHECK: slti $4, $5, -32768 # encoding: [0x00,0x80,0xa4,0x28]
slt $4, $5, 0 slt $4, $5, 0
# CHECK: slti $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x28] # CHECK: slti $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x28]
slt $4, $5, 0xFFFF slt $4, $5, 0xFFFF
# CHECK: ori $4, $zero, 65535 # encoding: [0xff,0xff,0x04,0x34] # CHECK: ori $4, $zero, 65535 # encoding: [0xff,0xff,0x04,0x34]
slt $4, $5, 0x10000 slt $4, $5, 0x10000
# CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c] # CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c]
# CHECK: slt $4, $4, $5 # encoding: [0x2a,0x20,0x85,0x00] # CHECK: slt $4, $4, $5 # encoding: [0x2a,0x20,0x85,0x00]
slt $4, $5, 0xFFFFFFFF slt $4, $5, 0xFFFFFFFF
# CHECK: slti $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x28] # CHECK: slti $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x28]
slt $4, $5, ~(0xf0000000|0x0f000000|0x000000f0)
# CHECK: lui $4, 255 # encoding: [0xff,0x00,0x04,0x3c]
# CHECK: ori $4, $4, 65295 # encoding: [0x0f,0xff,0x84,0x34]
# CHECK: slt $4, $4, $5 # encoding: [0x2a,0x20,0x85,0x00]
sltu $4, $5, -0x80000000 sltu $4, $5, -0x80000000
# CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c] # CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c]
# CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00] # CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
sltu $4, $5, -0x8001 sltu $4, $5, -0x8001
# CHECK: lui $4, 65535 # encoding: [0xff,0xff,0x04,0x3c] # CHECK: lui $4, 65535 # encoding: [0xff,0xff,0x04,0x3c]
# CHECK: ori $4, $4, 32767 # encoding: [0xff,0x7f,0x84,0x34] # CHECK: ori $4, $4, 32767 # encoding: [0xff,0x7f,0x84,0x34]
# CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00] # CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
sltu $4, $5, -0x8000 sltu $4, $5, -0x8000
# CHECK: sltiu $4, $5, -32768 # encoding: [0x00,0x80,0xa4,0x2c] # CHECK: sltiu $4, $5, -32768 # encoding: [0x00,0x80,0xa4,0x2c]
sltu $4, $5, 0 sltu $4, $5, 0
# CHECK: sltiu $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x2c] # CHECK: sltiu $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x2c]
sltu $4, $5, 0xFFFF sltu $4, $5, 0xFFFF
# CHECK: ori $4, $zero, 65535 # encoding: [0xff,0xff,0x04,0x34] # CHECK: ori $4, $zero, 65535 # encoding: [0xff,0xff,0x04,0x34]
sltu $4, $5, 0x10000 sltu $4, $5, 0x10000
# CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c] # CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c]
# CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00] # CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
sltu $4, $5, 0xFFFFFFFF sltu $4, $5, 0xFFFFFFFF
# CHECK: sltiu $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x2c] # CHECK: sltiu $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x2c]
sltu $4, $5, ~(0xf0000000|0x0f000000|0x000000f0)
# CHECK: lui $4, 255 # encoding: [0xff,0x00,0x04,0x3c]
# CHECK: ori $4, $4, 65295 # encoding: [0x0f,0xff,0x84,0x34]
# CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
xor $4, -0x80000000 xor $4, -0x80000000
# CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c] # CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c]
# CHECK: xor $4, $4, $1 # encoding: [0x26,0x20,0x81,0x00] # CHECK: xor $4, $4, $1 # encoding: [0x26,0x20,0x81,0x00]
xor $4, -0x8001 xor $4, -0x8001
# CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c] # CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c]
# CHECK: ori $1, $1, 32767 # encoding: [0xff,0x7f,0x21,0x34] # CHECK: ori $1, $1, 32767 # encoding: [0xff,0x7f,0x21,0x34]
# CHECK: xor $4, $4, $1 # encoding: [0x26,0x20,0x81,0x00] # CHECK: xor $4, $4, $1 # encoding: [0x26,0x20,0x81,0x00]
xor $4, -0x8000 xor $4, -0x8000
# CHECK: addiu $1, $zero, -32768 # encoding: [0x00,0x80,0x01,0x24] # CHECK: addiu $1, $zero, -32768 # encoding: [0x00,0x80,0x01,0x24]
xor $4, 0 xor $4, 0
# CHECK: xori $4, $4, 0 # encoding: [0x00,0x00,0x84,0x38] # CHECK: xori $4, $4, 0 # encoding: [0x00,0x00,0x84,0x38]
xor $4, 0xFFFF xor $4, 0xFFFF
# CHECK: xori $4, $4, 65535 # encoding: [0xff,0xff,0x84,0x38] # CHECK: xori $4, $4, 65535 # encoding: [0xff,0xff,0x84,0x38]
xor $4, 0x10000 xor $4, 0x10000
# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] # CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
# CHECK: xor $4, $4, $1 # encoding: [0x26,0x20,0x81,0x00] # CHECK: xor $4, $4, $1 # encoding: [0x26,0x20,0x81,0x00]
xor $4, 0xFFFFFFFF xor $4, 0xFFFFFFFF
# CHECK: addiu $1, $zero, -1 # encoding: [0xff,0xff,0x01,0x24] # CHECK: addiu $1, $zero, -1 # encoding: [0xff,0xff,0x01,0x24]
# CHECK: xor $4, $4, $1 # encoding: [0x26,0x20,0x81,0x00] # CHECK: xor $4, $4, $1 # encoding: [0x26,0x20,0x81,0x00]
xor $4, ~(0xf0000000|0x0f000000|0x000000f0)
# CHECK: lui $1, 255 # encoding: [0xff,0x00,0x01,0x3c]
# CHECK: ori $1, $1, 65295 # encoding: [0x0f,0xff,0x21,0x34]
# CHECK: xor $4, $4, $1 # encoding: [0x26,0x20,0x81,0x00]
xor $4, $5, -0x80000000 xor $4, $5, -0x80000000
# CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c] # CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c]
# CHECK: xor $4, $4, $5 # encoding: [0x26,0x20,0x85,0x00] # CHECK: xor $4, $4, $5 # encoding: [0x26,0x20,0x85,0x00]
xor $4, $5, -0x8001 xor $4, $5, -0x8001
# CHECK: lui $4, 65535 # encoding: [0xff,0xff,0x04,0x3c] # CHECK: lui $4, 65535 # encoding: [0xff,0xff,0x04,0x3c]
# CHECK: ori $4, $4, 32767 # encoding: [0xff,0x7f,0x84,0x34] # CHECK: ori $4, $4, 32767 # encoding: [0xff,0x7f,0x84,0x34]
# CHECK: xor $4, $4, $5 # encoding: [0x26,0x20,0x85,0x00] # CHECK: xor $4, $4, $5 # encoding: [0x26,0x20,0x85,0x00]
xor $4, $5, -0x8000 xor $4, $5, -0x8000
# CHECK: addiu $4, $zero, -32768 # encoding: [0x00,0x80,0x04,0x24] # CHECK: addiu $4, $zero, -32768 # encoding: [0x00,0x80,0x04,0x24]
# CHECK: xor $4, $4, $5 # encoding: [0x26,0x20,0x85,0x00] # CHECK: xor $4, $4, $5 # encoding: [0x26,0x20,0x85,0x00]
xor $4, $5, 0 xor $4, $5, 0
# CHECK: xori $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x38] # CHECK: xori $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x38]
xor $4, $5, 0xFFFF xor $4, $5, 0xFFFF
# CHECK: xori $4, $5, 65535 # encoding: [0xff,0xff,0xa4,0x38] # CHECK: xori $4, $5, 65535 # encoding: [0xff,0xff,0xa4,0x38]
xor $4, $5, 0x10000 xor $4, $5, 0x10000
# CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c] # CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c]
# CHECK: xor $4, $4, $5 # encoding: [0x26,0x20,0x85,0x00] # CHECK: xor $4, $4, $5 # encoding: [0x26,0x20,0x85,0x00]
xor $4, $5, 0xFFFFFFFF xor $4, $5, 0xFFFFFFFF
# CHECK: addiu $4, $zero, -1 # encoding: [0xff,0xff,0x04,0x24] # CHECK: addiu $4, $zero, -1 # encoding: [0xff,0xff,0x04,0x24]
# CHECK: xor $4, $4, $5 # encoding: [0x26,0x20,0x85,0x00] # CHECK: xor $4, $4, $5 # encoding: [0x26,0x20,0x85,0x00]
xor $4, $5, ~(0xf0000000|0x0f000000|0x000000f0)
# CHECK: lui $4, 255 # encoding: [0xff,0x00,0x04,0x3c]
# CHECK: ori $4, $4, 65295 # encoding: [0x0f,0xff,0x84,0x34]
# CHECK: xor $4, $4, $5 # encoding: [0x26,0x20,0x85,0x00]