[X86][Disassembler] Added SALC instruction

[craig.topper]

Do other assemblers/disassembler handle this instruction? Its not officially documented and I wasn't able to determine for sure what other tools do. For ffreep I at least stumbled onto postings about gcc emitting it and AMD has or had it in the optimization manual.

I also noticed sandpile.org says salc doesn't work in 64-bit mode.

[cray]

I know we have seen it in production code, but I can't remember what generated it currently. I just tested it with fasm and it assembled correctly. I was able to then disassemble it with IDA, and capstone.

Here is some good documentation on the instruction.
http://www.rcollins.org/secrets/opcodes/SALC.html

[craig.topper]

lib/Target/X86/X86InstrCMovSetCC.td

113

I think we need a Requires<[Not64BitMode]> here. sandpile.org and http://www.agner.org/optimize/instruction_tables.pdf both indicate its not available in 64-bit mode.

Can you also add a comment that's it undocumented just so its obvious why you can't find it in Intel or AMD official docs.

[majnemer]

In D29201#658545, @craig.topper wrote:

Do other assemblers/disassembler handle this instruction? Its not officially documented and I wasn't able to determine for sure what other tools do. For ffreep I at least stumbled onto postings about gcc emitting it and AMD has or had it in the optimization manual.

I also noticed sandpile.org says salc doesn't work in 64-bit mode.

FWIW, xed knows about salc: https://github.com/intelxed/xed/blob/eb45a282de284ec2574e2b54460b37b7e587996c/datafiles/xed-isa.txt#L8011

[cray]

Added Requires<[Not64BitMode]> to the SALC instruction, and added a comment saying that it is an undocumented instruction.

[craig.topper]

LGTM

lib/Target/X86/X86InstrCMovSetCC.td

 defm SETNS : SETCC<0x99, "setns", X86_COND_NS>;  // is not signed
 defm SETP  : SETCC<0x9A, "setp",  X86_COND_P>;   // is parity bit set
 defm SETNP : SETCC<0x9B, "setnp", X86_COND_NP>;  // is parity bit not set
 defm SETL  : SETCC<0x9C, "setl",  X86_COND_L>;   // signed less than
 defm SETGE : SETCC<0x9D, "setge", X86_COND_GE>;  // signed greater or equal
 defm SETLE : SETCC<0x9E, "setle", X86_COND_LE>;  // signed less than or equal
 defm SETG  : SETCC<0x9F, "setg",  X86_COND_G>;   // signed greater than
 
+let Uses = [EFLAGS], Defs = [AL] in {
+  def SALC : I<0xD6, RawFrm, (outs), (ins), "salc", []>;
+}

test/MC/Disassembler/X86/simple-tests.txt

 0xc4 0x42 0x1b 0xf7 0xd3
 
 # CHECK: shrxq %r12, (%rax), %r10
 0xc4 0x62 0x9b 0xf7 0x10
 
 # CHECK: shrxq %r12, %r11, %r10
 0xc4 0x42 0x9b 0xf7 0xd3
 
+# CHECK: salc
+0xd6
+
 # CHECK: vfmadd132ps %xmm11, %xmm12, %xmm10
 0xc4 0x42 0x19 0x98 0xd3
 
 # CHECK: vfmadd132pd %xmm11, %xmm12, %xmm10
 0xc4 0x42 0x99 0x98 0xd3
 
 # CHECK: vfmadd132ps %ymm11, %ymm12, %ymm10
 0xc4 0x42 0x1d 0x98 0xd3

test/MC/Disassembler/X86/x86-16.txt

 0x66 0x9d
 
 # CHECK: pushfl
 0x66 0x9c
 
 # CHECK: popfl
 0x66 0x9d
 
+# CHECK: salc
+0xd6
+
 # CHECK: setb %bl
 0x0f 0x92 0xc3
 
 # CHECK: setb %bl
 0x0f 0x92 0xc3
 
 # CHECK: setae %bl
 0x0f 0x93 0xc3

test/MC/X86/x86-32-coverage.s

 // CHECK: std
 // CHECK:  encoding: [0xfd]
           std
 
 // CHECK: sti
 // CHECK:  encoding: [0xfb]
           sti
 
+// CHECK: salc
+// CHECK:  encoding: [0xd6]
+          salc
+
 // CHECK: addb  $254, 3735928559(%ebx,%ecx,8)
 // CHECK:  encoding: [0x80,0x84,0xcb,0xef,0xbe,0xad,0xde,0xfe]
           addb  $0xfe,0xdeadbeef(%ebx,%ecx,8)
 
 // CHECK: addb  $254, 69
 // CHECK:  encoding: [0x80,0x05,0x45,0x00,0x00,0x00,0xfe]
           addb  $0xfe,0x45