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Differential D29193

[X86] Adding FFREEP instruction.
ClosedPublic

Authored by cray on Jan 26 2017, 12:28 PM.

Details

Reviewers
craig.topper
Commits
rG535e7d1547d1: [X86] Adding FFREEP instruction.
rL293314: [X86] Adding FFREEP instruction.
Summary

Small change to get the FREEP instruction to decode properly.

Diff Detail

Event Timeline

cray created this revision.Jan 26 2017, 12:28 PM
Harbormaster completed remote builds in B3323: Diff 85946.Jan 26 2017, 12:28 PM
cray updated this revision to Diff 85951.Jan 26 2017, 1:06 PM

Fixing issue with the diff context

Harbormaster completed remote builds in B3326: Diff 85951.Jan 26 2017, 1:06 PM
cray set the repository for this revision to rL LLVM.Jan 26 2017, 1:10 PM
cray added a subscriber: llvm-commits.Jan 26 2017, 1:20 PM
craig.topper accepted this revision.Jan 26 2017, 11:22 PM

LGTM

This revision is now accepted and ready to land.Jan 26 2017, 11:22 PM
cray closed this revision.Jan 27 2017, 10:14 AM
Closed by commit rL293314: [X86] Adding FFREEP instruction. (authored by cray). · Explain WhyJan 27 2017, 10:14 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
X86/
X86InstrFPStack.td
X86InstrFPStack.td (revision 293201)
3 lines
test/
MC/
Disassembler/
X86/
fp-stack.txt
fp-stack.txt (revision 293201)
24 lines
X86/
x86-32-coverage.s
x86-32-coverage.s (revision 293201)
4 lines

Diff 85951

lib/Target/X86/X86InstrFPStack.td

Show First 20 Lines • Show All 625 Lines • ▼ Show 20 Linesdef FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
Sched<[WriteLoad]>; Sched<[WriteLoad]>;
// FPU control instructions // FPU control instructions
let SchedRW = [WriteMicrocoded] in { let SchedRW = [WriteMicrocoded] in {
let Defs = [FPSW] in let Defs = [FPSW] in
def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", [], IIC_FNINIT>; def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", [], IIC_FNINIT>;
def FFREE : FPI<0xDD, MRM0r, (outs), (ins RST:$reg), def FFREE : FPI<0xDD, MRM0r, (outs), (ins RST:$reg),
"ffree\t$reg", IIC_FFREE>; "ffree\t$reg", IIC_FFREE>;
def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RST:$reg),
"ffreep\t$reg", IIC_FFREE>;
// Clear exceptions // Clear exceptions
let Defs = [FPSW] in let Defs = [FPSW] in
def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", [], IIC_FNCLEX>; def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", [], IIC_FNCLEX>;
} // SchedRW } // SchedRW
// Operandless floating-point instructions for the disassembler. // Operandless floating-point instructions for the disassembler.
let SchedRW = [WriteMicrocoded] in { let SchedRW = [WriteMicrocoded] in {
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test/MC/Disassembler/X86/fp-stack.txt

Show First 20 Lines • Show All 979 Lines • ▼ Show 20 Lines
0xde,0xfd 0xde,0xfd
# CHECK: fdivrp %st(6) # CHECK: fdivrp %st(6)
0xde,0xfe 0xde,0xfe
# CHECK: fdivrp %st(7) # CHECK: fdivrp %st(7)
0xde,0xff 0xde,0xff
# CHECK: ffreep %st(0)
0xdf,0xc0
# CHECK: ffreep %st(1)
0xdf,0xc1
# CHECK: ffreep %st(2)
0xdf,0xc2
# CHECK: ffreep %st(3)
0xdf,0xc3
# CHECK: ffreep %st(4)
0xdf,0xc4
# CHECK: ffreep %st(5)
0xdf,0xc5
# CHECK: ffreep %st(6)
0xdf,0xc6
# CHECK: ffreep %st(7)
0xdf,0xc7
# CHECK: fnstsw %ax # CHECK: fnstsw %ax
0xdf,0xe0 0xdf,0xe0
# CHECK: fucompi %st(0) # CHECK: fucompi %st(0)
0xdf,0xe8 0xdf,0xe8
# CHECK: fucompi %st(1) # CHECK: fucompi %st(1)
0xdf,0xe9 0xdf,0xe9
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test/MC/X86/x86-32-coverage.s

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,741 Lines • ▼ Show 20 Lines
// CHECK: frstor 32493 // CHECK: frstor 32493
// CHECK: encoding: [0xdd,0x25,0xed,0x7e,0x00,0x00] // CHECK: encoding: [0xdd,0x25,0xed,0x7e,0x00,0x00]
frstor 0x7eed frstor 0x7eed
// CHECK: ffree %st(2) // CHECK: ffree %st(2)
// CHECK: encoding: [0xdd,0xc2] // CHECK: encoding: [0xdd,0xc2]
ffree %st(2) ffree %st(2)
// CHECK: ffreep %st(2)
// CHECK: encoding: [0xdf,0xc2]
ffreep %st(2)
// CHECK: fnop // CHECK: fnop
// CHECK: encoding: [0xd9,0xd0] // CHECK: encoding: [0xd9,0xd0]
fnop fnop
// CHECK: invd // CHECK: invd
// CHECK: encoding: [0x0f,0x08] // CHECK: encoding: [0x0f,0x08]
invd invd
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