[PowerPC][Altivec] Add vmr extended mnemonic

[brunoalr]

Summary

vmr v1,v2 is an alias to vor v1,v2,v2

[brunoalr]

Will add nemanjai's patch on mfvrd.

[brunoalr]

mfvrd with VR registers is an alias to mfvsrd with VSR registers.

Patch by nemanjai

[nemanjai]

lib/Target/PowerPC/PPCInstrVSX.td

1450 ↗

(On Diff #85783)

@hfinkel Do you think this is an acceptable way to get this support implemented? Or do you have a preferred suggestion? Maybe some custom handling of the register operand (or even the mnemonic itself) in the Asm parser/printer or something along those lines...

Once we decide how we want to approach this, we can add a test case.

[hfinkel]

In D29133#656541, @brunoalr wrote:

mfvrd with VR registers is an alias to mfvsrd with VSR registers.

Patch by nemanjai

Why did you fold these together? Can we just do the vor -> vmr alias, and then worry about the mfvrd change separately? The vor -> vmr LGTM, so if you can pull these apart, please commit that part.

lib/Target/PowerPC/PPCInstrVSX.td

1450 ↗

(On Diff #85783)

One of these should be mfvsrd?

[brunoalr]

In D29133#657494, @hfinkel wrote:

In D29133#656541, @brunoalr wrote:

mfvrd with VR registers is an alias to mfvsrd with VSR registers.

Patch by nemanjai

Why did you fold these together? Can we just do the vor -> vmr alias, and then worry about the mfvrd change separately? The vor -> vmr LGTM, so if you can pull these apart, please commit that part.

Yes, we can do them separately. I'll make the necessary changes to this diff. I don't have commit permissions yet, but I'll prepare the vor -> vmr diff.

[nemanjai]

Why did you fold these together? Can we just do the vor -> vmr alias, and then worry about the mfvrd change separately? The vor -> vmr LGTM, so if you can pull these apart, please commit that part.

Sorry, this is probably my fault. They needed these two extended mnemonics and I recommended they publish just one patch for them.
I'll commit the vor -> vmr patch. @brunoalr please post the mfvrd one separately.

[nemanjai]

lib/Target/PowerPC/PPCInstrVSX.td

1450 ↗

(On Diff #85783)

The asm string that we want to match when parsing asm is mfvrd. However, doing so will produce an instruction with a VR input. So if we also use this alias for printing, we'll print $XT + 32. That's why the zero for the Emit flag.

In a way, this is a hack for the InstAlias class. We need to read the input and treat it as a different register class (with different numbering).

[brunoalr]

In D29133#657501, @nemanjai wrote:

Why did you fold these together? Can we just do the vor -> vmr alias, and then worry about the mfvrd change separately? The vor -> vmr LGTM, so if you can pull these apart, please commit that part.

Sorry, this is probably my fault. They needed these two extended mnemonics and I recommended they publish just one patch for them.
I'll commit the vor -> vmr patch. @brunoalr please post the mfvrd one separately.

@nemanjai here: https://reviews.llvm.org/D29177

[brunoalr]

• Remove mfvrd portion

[brunoalr]

• Add vmr tests and remove mfvrd leftover code

[brunoalr]

@hfinkel I updated this diff to include only the vmr portion and added a test here as well

@nemanjai @kbarton please continue the discussion on mfvrd here: D29177

[brunoalr]

Gently pinging :)

[nemanjai]

Will commit this as we're all in agreement on the part that remains in this patch now.

llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td

 }
 }
 } // VALU Operations.
 
 //===----------------------------------------------------------------------===//
 // Additional Altivec Patterns
 //
 
+// Extended mnemonics
+def : InstAlias<"vmr $vD, $vA", (VOR vrrc:$vD, vrrc:$vA, vrrc:$vA)>;
+
 // Loads.
 def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;
 
 // Stores.
 def : Pat<(store v4i32:$rS, xoaddr:$dst),
           (STVX $rS, xoaddr:$dst)>;
 
 // Bit conversions.

llvm/trunk/test/CodeGen/PowerPC/select-i1-vs-i1.ll

entry:
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floatslt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vor 2, 3, 3
+; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <4 x float> @testv4floatult(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floatult
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vor 2, 3, 3
+; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <4 x float> @testv4floatsle(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floatsle
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vor 2, 3, 3
+; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <4 x float> @testv4floatule(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floatule
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vor 2, 3, 3
+; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <4 x float> @testv4floateq(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floateq
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: bc 12, [[REG1]], .LBB[[BB1:[0-9_]+]]
-; CHECK: vor 3, 2, 2
+; CHECK: vmr 3, 2
 ; CHECK: .LBB[[BB1]]
-; CHECK: vor 2, 3, 3
+; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <4 x float> @testv4floatsge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floatsge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vor 2, 3, 3
+; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <4 x float> @testv4floatuge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floatuge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vor 2, 3, 3
+; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <4 x float> @testv4floatsgt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floatsgt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vor 2, 3, 3
+; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <4 x float> @testv4floatugt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floatugt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vor 2, 3, 3
+; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <4 x float> @testv4floatne(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floatne
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vor 2, 3, 3
+; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define ppc_fp128 @testppc_fp128eq(ppc_fp128 %c1, ppc_fp128 %c2, ppc_fp128 %c3, ppc_fp128 %c4, ppc_fp128 %a1, ppc_fp128 %a2) #0 {
 entry:
   %cmp1 = fcmp oeq ppc_fp128 %c3, %c4
   %cmp3tmp = fcmp oeq ppc_fp128 %c1, %c2
   %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
entry:
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doubleslt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vor 2, 3, 3
+; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doubleult(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doubleult
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vor 2, 3, 3
+; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doublesle(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doublesle
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vor 2, 3, 3
+; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doubleule(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doubleule
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vor 2, 3, 3
+; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doubleeq(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doubleeq
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: bc 12, [[REG1]], .LBB[[BB55:[0-9_]+]]
-; CHECK: vor 3, 2, 2
+; CHECK: vmr 3, 2
 ; CHECK: .LBB[[BB55]]
-; CHECK: vor 2, 3, 3
+; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doublesge(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doublesge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vor 2, 3, 3
+; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doubleuge(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doubleuge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vor 2, 3, 3
+; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doublesgt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doublesgt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vor 2, 3, 3
+; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doubleugt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doubleugt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vor 2, 3, 3
+; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doublene(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doublene
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vor 2, 3, 3
+; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <4 x double> @testqv4doubleslt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp slt i1 %cmp3tmp, %cmp1

llvm/trunk/test/CodeGen/PowerPC/vsx-args.ll

 ; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=+vsx | FileCheck %s
 ; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 | \
 ; RUN:   FileCheck -check-prefix=CHECK-FISL %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 declare <2 x double> @sv(<2 x double>, <2 x i64>, <4 x float>) #0
 
 define <2 x double> @main(<4 x float> %a, <2 x double> %b, <2 x i64> %c) #1 {
 entry:
   %ca = tail call <2 x double> @sv(<2 x double> %b, <2 x i64> %c,  <4 x float> %a)
   %v = fadd <2 x double> %ca, <double 1.0, double 1.0>
   ret <2 x double> %v
 
 ; CHECK-LABEL: @main
-; CHECK-DAG: vor [[V:[0-9]+]], 2, 2
-; CHECK-DAG: vor 2, 3, 3
-; CHECK-DAG: vor 3, 4, 4
-; CHECK-DAG: vor 4, [[V]], [[V]]
+; CHECK-DAG: vmr [[V:[0-9]+]], 2
+; CHECK-DAG: vmr 2, 3
+; CHECK-DAG: vmr 3, 4
+; CHECK-DAG: vmr 4, [[V]]
 ; CHECK: bl sv
 ; CHECK: lxvd2x [[VC:[0-9]+]],
 ; CHECK: xvadddp 34, 34, [[VC]]
 ; CHECK: blr
 
 ; CHECK-FISL-LABEL: @main
 ; CHECK-FISL: stxvd2x 34
-; CHECK-FISL: vor 2, 3, 3
-; CHECK-FISL: vor 3, 4, 4
+; CHECK-FISL: vmr 2, 3
+; CHECK-FISL: vmr 3, 4
 ; CHECK-FISL: lxvd2x 36
 ; CHECK-FISL: bl sv
 ; CHECK-FISL: lxvd2x [[VC:[0-9]+]],
 ; CHECK-FISL: xvadddp 34, 34, [[VC]]
 ; CHECK-FISL: blr
 }
 
 attributes #0 = { noinline nounwind readnone }
 attributes #1 = { nounwind }
 

llvm/trunk/test/CodeGen/PowerPC/vsx-infl-copy1.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 @ub = external global [1024 x i32], align 4
 @uc = external global [1024 x i32], align 4
 
 ; Function Attrs: noinline nounwind
 define <4 x i32> @_Z8example9Pj(<4 x i32>* %addr1, i64 %input1, i64 %input2) #0 {
 entry:
   br label %vector.body
 
 ; CHECK-LABEL: @_Z8example9Pj
-; CHECK: vor
-; CHECK: vor
-; CHECK: vor
-; CHECK: vor
-; CHECK: vor
-; CHECK: vor
-; CHECK: vor
-; CHECK: vor
-; CHECK: vor
+; CHECK: vmr
+; CHECK: vmr
+; CHECK: vmr
+; CHECK: vmr
+; CHECK: vmr
+; CHECK: vmr
+; CHECK: vmr
+; CHECK: vmr
+; CHECK: vmr
 
 vector.body:                                      ; preds = %vector.body, %entry
   %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
   %vec.phi = phi <4 x i32> [ zeroinitializer, %entry ], [ %43, %vector.body ]
   %vec.phi20 = phi <4 x i32> [ zeroinitializer, %entry ], [ %44, %vector.body ]
   %vec.phi21 = phi <4 x i32> [ zeroinitializer, %entry ], [ %45, %vector.body ]
   %vec.phi23 = phi <4 x i32> [ zeroinitializer, %entry ], [ %46, %vector.body ]
   %vec.phi24 = phi <4 x i32> [ zeroinitializer, %entry ], [ %47, %vector.body ]

llvm/trunk/test/MC/PowerPC/ppc64-encoding-vmx.s

 # CHECK-LE: vorc 2, 3, 4                    # encoding: [0x44,0x25,0x43,0x10]
             vorc 2, 3, 4
 # CHECK-BE: vnor 2, 3, 4                    # encoding: [0x10,0x43,0x25,0x04]
 # CHECK-LE: vnor 2, 3, 4                    # encoding: [0x04,0x25,0x43,0x10]
             vnor 2, 3, 4
 # CHECK-BE: vor 2, 3, 4                     # encoding: [0x10,0x43,0x24,0x84]
 # CHECK-LE: vor 2, 3, 4                     # encoding: [0x84,0x24,0x43,0x10]
             vor 2, 3, 4
+# CHECK-BE: vmr 2, 3                        # encoding: [0x10,0x43,0x1c,0x84]
+# CHECK-LE: vmr 2, 3                        # encoding: [0x84,0x1c,0x43,0x10]
+            vmr 2, 3
 # CHECK-BE: vxor 2, 3, 4                    # encoding: [0x10,0x43,0x24,0xc4]
 # CHECK-LE: vxor 2, 3, 4                    # encoding: [0xc4,0x24,0x43,0x10]
             vxor 2, 3, 4
 
 # Vector integer rotate and shift instructions
 
 # CHECK-BE: vrlb 2, 3, 4                    # encoding: [0x10,0x43,0x20,0x04]
 # CHECK-LE: vrlb 2, 3, 4                    # encoding: [0x04,0x20,0x43,0x10]