Regression in 4.0-rc: SPARC: allow %f-registers for inline-assembly

[pboettch]

Summary

This reverts the reverts done in svn 278511. It was
part of 3.9-release (where it worked for me)
and does not exist anymore in 4.0-rc.

Unfortunately there is no explanation given in the
commit as to why it was removed.

A accompanying change for clang will be provided.

[pboettch]

Added test-code in inlineasm.ll

[jyknight]

Is it desirable for the supported register constraints to have the same meaning as in GCC, and this is not: GCC defines 'f' as the lower fp regs, and 'e' as all of the fp regs. (Those are only actually different for sparcv9, of course.)

Also, you'll need to the inlineasm docs in the LangRef to add the new constraint.

[pboettch]

OK, I will update my changes in regards to your comment, but it'll take some time.

Have it been these missing things which made you reverting the %f changes for 4.0 made by Chris? For me this fixes a regression, because in 3.9 it worked. (but broke sparcv9?)

The more I think about it, the less I know how to implement it correctly. I'll try nevertheless.

[jyknight]

In D29116#657283, @pboettch wrote:

Have it been these missing things which made you reverting the %f changes for 4.0 made by Chris? For me this fixes a regression, because in 3.9 it worked. (but broke sparcv9?)

The %f bit was an unrelated change that was committed along with a bunch of other unrelated stuff, and should not have been.

[pboettch]

I added a LangRef.rst regarding inline asm usage of %f for Sparc(V8).

For the code-part, I actually don't know what to do. I'm using a LEON which is a SparcV8 and it does not seem to have %e registers.

I'm willing to change things to get the part I can use and test integrated, but I'd need some more help.

[jyknight]

I've fixed up the patch and applied it, thanks!

lib/Target/Sparc/SparcISelLowering.cpp

   if (Constraint.size() == 1) {
     switch (Constraint[0]) {
     default:  break;
-    case 'r': return C_RegisterClass;
+    case 'r':
+    case 'f':
+      return C_RegisterClass;
     case 'I': // SIMM13
       return C_Other;
     }

                                                   MVT VT) const {
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {
+    case 'f':
+      if (VT == MVT::f32)
+        return std::make_pair(0U, &SP::FPRegsRegClass);
+      else if (VT == MVT::f64)
+        return std::make_pair(0U, &SP::DFPRegsRegClass);
+      else if (VT == MVT::f128)
+        return std::make_pair(0U, &SP::QFPRegsRegClass);
+
+      llvm_unreachable("Unknown ValueType for f-register-type!");
+
+      break;
+
     case 'r':
       if (VT == MVT::v2i32)
         return std::make_pair(0U, &SP::IntPairRegClass);

test/CodeGen/SPARC/inlineasm.ll

   %0 = call i64 asm sideeffect "xor $1, %g0, $0", "=r,0,~{i1}"(i64 5);
   ret i64 %0
 }
+
+;; Ensures that inline-asm accepts and uses %f registers
+; CHECK-LABEL: fabsf
+; CHECK: fabss  %f0, %f0
+define float @fabsf(float) local_unnamed_addr #2 {
+entry:
+  %1 = tail call float asm sideeffect "fabss  $1, $0;", "=f,f"(float %0) #7
+  ret float %1
+}