[XRay][AArch64] More staging for tail call support in XRay on AArch64 - in LLVM

[rSerge]

Summary

This patch prepares more for tail call support in XRay. Until the logging part supports tail calls, this is just staging, so it seems LLVM part is mostly ready with this patch.
Related: https://reviews.llvm.org/D28948 (compiler-rt)

[dberris]

test/CodeGen/AArch64/xray-tail-call-sled.ll

30

You probably want to make sure that you have the instrumentation map for this function and the one below.

[rSerge]

test/CodeGen/AArch64/xray-tail-call-sled.ll

30

I thought about this, but this is already tested in llvm\test\CodeGen\AArch64\xray-attribute-instrumentation.ll. Why to duplicate here the testing of instrumentation map emission?

[dberris]

test/CodeGen/AArch64/xray-tail-call-sled.ll

30

That's fair -- I was thinking about the off-chance that maybe the tail sled's entry is not emitted as part of the table (or that it has a different type). Adding a test specifically for the tail sled's entry in the map with the correct type gets us coverage to make sure we don't break that part again.

[rengolin]

lib/Target/AArch64/AArch64InstrInfo.cpp

1630

This is in line with what the x86 and hexagon back-ends already have. Should be fine.

[rSerge]

Added checking for xray instrumentation map emission in the test.

[rSerge]

Reached mainline in revision 293080.

lib/Target/AArch64/AArch64InstrInfo.h

public:
   bool isLdStPairSuppressed(const MachineInstr &MI) const;
 
   /// Return true if this is an unscaled load/store.
   bool isUnscaledLdSt(unsigned Opc) const;
 
   /// Return true if this is an unscaled load/store.
   bool isUnscaledLdSt(MachineInstr &MI) const;
 
+  bool isTailCall(const MachineInstr &Inst) const override;
+
   static bool isPairableLdStInst(const MachineInstr &MI) {
     switch (MI.getOpcode()) {
     default:
       return false;
     // Scaled instructions.
     case AArch64::STRSui:
     case AArch64::STRDui:
     case AArch64::STRQui:

lib/Target/AArch64/AArch64InstrInfo.cpp

case AArch64::LDURSHWi:
     return true;
   }
 }
 
 bool AArch64InstrInfo::isUnscaledLdSt(MachineInstr &MI) const {
   return isUnscaledLdSt(MI.getOpcode());
 }
 
+bool AArch64InstrInfo::isTailCall(const MachineInstr &Inst) const
+{
+  switch (Inst.getOpcode()) {
+  case AArch64::TCRETURNdi:
+  case AArch64::TCRETURNri:
+    return true;
+  default:
+    return false;
+  }
+}
+
 // Is this a candidate for ld/st merging or pairing?  For example, we don't
 // touch volatiles or load/stores that have a hint to avoid pair formation.
 bool AArch64InstrInfo::isCandidateToMergeOrPair(MachineInstr &MI) const {
   // If this is a volatile load/store, don't mess with it.
   if (MI.hasOrderedMemoryRef())
     return false;
 
   // Make sure this is a reg+imm (as opposed to an address reloc).

test/CodeGen/AArch64/xray-tail-call-sled.ll

+; RUN: llc -filetype=asm -o - -mtriple=aarch64-linux-gnu < %s | FileCheck %s
+
+define i32 @callee() nounwind noinline uwtable "function-instrument"="xray-always" {
+; CHECK:       .p2align 2
+; CHECK-LABEL: .Lxray_sled_0:
+; CHECK-NEXT:  b  #32
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-LABEL: .Ltmp0:
+  ret i32 0
+; CHECK-NEXT:  mov  w0, wzr
+; CHECK-NEXT:  .p2align 2
+; CHECK-LABEL: .Lxray_sled_1:
+; CHECK-NEXT:  b  #32
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-LABEL: .Ltmp1:
+; CHECK-NEXT:  ret
+}
+; CHECK:       .p2align 4
+; CHECK-NEXT:  .xword .Lxray_synthetic_0
+; CHECK-NEXT:  .section xray_instr_map,{{.*}}
+; CHECK-LABEL: Lxray_synthetic_0:
+; CHECK:       .xword .Lxray_sled_0
+; CHECK:       .xword .Lxray_sled_1
+
+define i32 @caller() nounwind noinline uwtable "function-instrument"="xray-always" {
+; CHECK:       .p2align 2
+; CHECK-LABEL: .Lxray_sled_2:
+; CHECK-NEXT:  b  #32
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-LABEL: .Ltmp2:
+; CHECK:       .p2align 2
+; CHECK-LABEL: .Lxray_sled_3:
+; CHECK-NEXT:  b  #32
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-LABEL: .Ltmp3:
+  %retval = tail call i32 @callee()
+; CHECK:       b  callee
+  ret i32 %retval
+}
+; CHECK:       .p2align 4
+; CHECK-NEXT:  .xword .Lxray_synthetic_1
+; CHECK-NEXT:  .section xray_instr_map,{{.*}}
+; CHECK-LABEL: Lxray_synthetic_1:
+; CHECK:       .xword .Lxray_sled_2
+; CHECK:       .xword .Lxray_sled_3