LiveIntervalAnalysis: Calculate liveness even if a superreg is reserved.

[MatzeB]

Summary

A register unit may be allocatable and non-reserved but some of the
register(tuples) built with it are reserved. We still need to calculate
liveness in this case.

[escha]

Confirmed this fixes the problem I was having.

[qcolombet]

LGTM.

[MatzeB]

So we don't really have a concept of reserving register units, we just reserve registers; This patch currenly considers a register unit as reserved if all the root registers are reserved. This turned out to be a bad idea for the X86 32bit mode which reserves BIL, SIL, ... but of course still wants to use the 16+32bit versions of those register.

So I tried changing this to a register unit is considered reserved if the roots and all their super registers are reserved. This fixes all X86 cases but now breaks a number of tests on PowerPC and Hexagon (fun times).

[kparzysz]

Could you update to r292836 (or later) and try again? Hexagon should start working.

[MatzeB]

In D28881#653926, @kparzysz wrote:

Could you update to r292836 (or later) and try again? Hexagon should start working.

Indeed its fixed now before I even started investigating. Woohoo, thanks that is cool!

(I started with PowerPC which looks like it needs a similar fix as Hexagon, but got interrupted by a meeting)

[MatzeB]

Fix for PowerPC submited as D29056

llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp

void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
   assert(LRCalc && "LRCalc not initialized.");
   LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
 
   // The physregs aliasing Unit are the roots and their super-registers.
   // Create all values as dead defs before extending to uses. Note that roots
   // may share super-registers. That's OK because createDeadDefs() is
   // idempotent. It is very rare for a register unit to have multiple roots, so
   // uniquing super-registers is probably not worthwhile.
+  bool IsReserved = true;
   for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
     for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
          Super.isValid(); ++Super) {
       unsigned Reg = *Super;
       if (!MRI->reg_empty(Reg))
         LRCalc->createDeadDefs(LR, Reg);
+      // A register unit is considered reserved if all its roots and all their
+      // super registers are reserved.
+      if (!MRI->isReserved(Reg))
+        IsReserved = false;
     }
   }
 
   // Now extend LR to reach all uses.
   // Ignore uses of reserved registers. We only track defs of those.
+  if (!IsReserved) {
     for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
       for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
            Super.isValid(); ++Super) {
         unsigned Reg = *Super;
-      if (!MRI->isReserved(Reg) && !MRI->reg_empty(Reg))
+        if (!MRI->reg_empty(Reg))
           LRCalc->extendToUses(LR, Reg);
       }
     }
+  }
 
   // Flush the segment set to the segment vector.
   if (UseSegmentSetForPhysRegs)
     LR.flushSegmentSet();
 }
 
 /// Precompute the live ranges of any register units that are live-in to an ABI
 /// block somewhere. Register values can appear without a corresponding def when

llvm/trunk/test/CodeGen/AArch64/live-interval-analysis.mir

+# RUN: llc -o /dev/null %s -mtriple=aarch64-darwin-ios -run-pass=liveintervals -debug-only=regalloc -precompute-phys-liveness 2>&1 | FileCheck %s
+# REQUIRES: asserts
+--- |
+  define void @reserved_reg_liveness() { ret void }
+...
+---
+# CHECK-LABEL: ********** INTERVALS **********
+# W29 is reserved, so we should only see dead defs
+# CHECK-DAG: W29 [0B,0d:{{[0-9]+}})[32r,32d:{{[0-9]+}})[64r,64d:{{[0-9]+}})
+# For normal registers like x28 we should see the full intervals
+# CHECK-DAG: W28 [0B,16r:{{[0-9]+}})[32r,48r:{{[0-9]+}})[48r,48d:{{[0-9]+}})
+# CHECK: # End machine code for function reserved_reg_liveness.
+name: reserved_reg_liveness
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: %x28_fp
+    %6 : xseqpairsclass = COPY %x28_fp
+    %x28_fp = COPY %6
+    %x28 = COPY %x28
+    %fp = COPY %fp
+...