DAG: Fold fneg into compare with constant into the constant

[arsenm]

Summary

fcmp (fneg x), c, pred -> fcmp x, -c, (swap pred)

InstCombine already does this.

[arsenm]

Add tests showing net improvement with multiple uses

[arsenm]

ping

[arsenm]

r293512

lib/CodeGen/SelectionDAG/TargetLowering.cpp

if (isa<ConstantFPSDNode>(N0.getNode())) {
 
     // Otherwise, we know the RHS is not a NaN.  Simplify the node to drop the
     // constant if knowing that the operand is non-nan is enough.  We prefer to
     // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
     // materialize 0.0.
     if (Cond == ISD::SETO || Cond == ISD::SETUO)
       return DAG.getSetCC(dl, VT, N0, N0, Cond);
 
+    // setcc (fneg x), C -> setcc swap(pred) x, -C
+    if (N0.getOpcode() == ISD::FNEG) {
+      ISD::CondCode SwapCond = ISD::getSetCCSwappedOperands(Cond);
+      if (DCI.isBeforeLegalizeOps() ||
+          isCondCodeLegal(SwapCond, N0.getSimpleValueType())) {
+        SDValue NegN1 = DAG.getNode(ISD::FNEG, dl, N0.getValueType(), N1);
+        return DAG.getSetCC(dl, VT, N0.getOperand(0), NegN1, SwapCond);
+      }
+    }
+
     // If the condition is not legal, see if we can find an equivalent one
     // which is legal.
     if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
       // If the comparison was an awkward floating-point == or != and one of
       // the comparison operands is infinity or negative infinity, convert the
       // condition to a less-awkward <= or >=.
       if (CFP->getValueAPF().isInfinity()) {
         if (CFP->getValueAPF().isNegative()) {

test/CodeGen/AMDGPU/setcc-fneg-constant.ll

+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
+
+; Test fcmp pred (fneg x), c -> fcmp (swapped pred) x, -c combine.
+
+; GCN-LABEL: {{^}}test_setcc_fneg_oeq_posk_f32:
+; GCN: v_cmp_eq_f32_e32 vcc, -4.0, v{{[0-9]+}}
+define void @test_setcc_fneg_oeq_posk_f32() #0 {
+  %a = load volatile float, float addrspace(1)* undef
+  %x = load volatile i32, i32 addrspace(1)* undef
+  %y = load volatile i32, i32 addrspace(1)* undef
+  %neg.a = fsub float -0.0, %a
+  %cmp = fcmp oeq float %neg.a, 4.0
+  %select = select i1 %cmp, i32 %x, i32 %y
+  store volatile i32 %select, i32 addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_setcc_fneg_ogt_posk_f32:
+; GCN: v_cmp_gt_f32_e32 vcc, -4.0, v{{[0-9]+}}
+define void @test_setcc_fneg_ogt_posk_f32() #0 {
+  %a = load volatile float, float addrspace(1)* undef
+  %x = load volatile i32, i32 addrspace(1)* undef
+  %y = load volatile i32, i32 addrspace(1)* undef
+  %neg.a = fsub float -0.0, %a
+  %cmp = fcmp ogt float %neg.a, 4.0
+  %select = select i1 %cmp, i32 %x, i32 %y
+  store volatile i32 %select, i32 addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_setcc_fneg_oge_posk_f32:
+; GCN: v_cmp_ge_f32_e32 vcc, -4.0, v{{[0-9]+}}
+define void @test_setcc_fneg_oge_posk_f32() #0 {
+  %a = load volatile float, float addrspace(1)* undef
+  %x = load volatile i32, i32 addrspace(1)* undef
+  %y = load volatile i32, i32 addrspace(1)* undef
+  %neg.a = fsub float -0.0, %a
+  %cmp = fcmp oge float %neg.a, 4.0
+  %select = select i1 %cmp, i32 %x, i32 %y
+  store volatile i32 %select, i32 addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_setcc_fneg_olt_posk_f32:
+; GCN: v_cmp_lt_f32_e32 vcc, -4.0, v{{[0-9]+}}
+define void @test_setcc_fneg_olt_posk_f32() #0 {
+  %a = load volatile float, float addrspace(1)* undef
+  %x = load volatile i32, i32 addrspace(1)* undef
+  %y = load volatile i32, i32 addrspace(1)* undef
+  %neg.a = fsub float -0.0, %a
+  %cmp = fcmp olt float %neg.a, 4.0
+  %select = select i1 %cmp, i32 %x, i32 %y
+  store volatile i32 %select, i32 addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_setcc_fneg_ole_posk_f32:
+; GCN: v_cmp_le_f32_e32 vcc, -4.0, v{{[0-9]+}}
+define void @test_setcc_fneg_ole_posk_f32() #0 {
+  %a = load volatile float, float addrspace(1)* undef
+  %x = load volatile i32, i32 addrspace(1)* undef
+  %y = load volatile i32, i32 addrspace(1)* undef
+  %neg.a = fsub float -0.0, %a
+  %cmp = fcmp ole float %neg.a, 4.0
+  %select = select i1 %cmp, i32 %x, i32 %y
+  store volatile i32 %select, i32 addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_setcc_fneg_one_posk_f32:
+; GCN: v_cmp_lg_f32_e32 vcc, -4.0, v{{[0-9]+}}
+define void @test_setcc_fneg_one_posk_f32() #0 {
+  %a = load volatile float, float addrspace(1)* undef
+  %x = load volatile i32, i32 addrspace(1)* undef
+  %y = load volatile i32, i32 addrspace(1)* undef
+  %neg.a = fsub float -0.0, %a
+  %cmp = fcmp one float %neg.a, 4.0
+  %select = select i1 %cmp, i32 %x, i32 %y
+  store volatile i32 %select, i32 addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_setcc_fneg_ueq_posk_f32:
+; GCN: v_cmp_nlg_f32_e32 vcc, -4.0, v{{[0-9]+}}
+define void @test_setcc_fneg_ueq_posk_f32() #0 {
+  %a = load volatile float, float addrspace(1)* undef
+  %x = load volatile i32, i32 addrspace(1)* undef
+  %y = load volatile i32, i32 addrspace(1)* undef
+  %neg.a = fsub float -0.0, %a
+  %cmp = fcmp ueq float %neg.a, 4.0
+  %select = select i1 %cmp, i32 %x, i32 %y
+  store volatile i32 %select, i32 addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_setcc_fneg_ugt_posk_f32:
+; GCN: v_cmp_nle_f32_e32 vcc, -4.0, v{{[0-9]+}}
+define void @test_setcc_fneg_ugt_posk_f32() #0 {
+  %a = load volatile float, float addrspace(1)* undef
+  %x = load volatile i32, i32 addrspace(1)* undef
+  %y = load volatile i32, i32 addrspace(1)* undef
+  %neg.a = fsub float -0.0, %a
+  %cmp = fcmp ugt float %neg.a, 4.0
+  %select = select i1 %cmp, i32 %x, i32 %y
+  store volatile i32 %select, i32 addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_setcc_fneg_uge_posk_f32:
+; GCN: v_cmp_nlt_f32_e32 vcc, -4.0, v{{[0-9]+}}
+define void @test_setcc_fneg_uge_posk_f32() #0 {
+  %a = load volatile float, float addrspace(1)* undef
+  %x = load volatile i32, i32 addrspace(1)* undef
+  %y = load volatile i32, i32 addrspace(1)* undef
+  %neg.a = fsub float -0.0, %a
+  %cmp = fcmp uge float %neg.a, 4.0
+  %select = select i1 %cmp, i32 %x, i32 %y
+  store volatile i32 %select, i32 addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_setcc_fneg_ult_posk_f32:
+; GCN: v_cmp_nge_f32_e32 vcc, -4.0, v{{[0-9]+}}
+define void @test_setcc_fneg_ult_posk_f32() #0 {
+  %a = load volatile float, float addrspace(1)* undef
+  %x = load volatile i32, i32 addrspace(1)* undef
+  %y = load volatile i32, i32 addrspace(1)* undef
+  %neg.a = fsub float -0.0, %a
+  %cmp = fcmp ult float %neg.a, 4.0
+  %select = select i1 %cmp, i32 %x, i32 %y
+  store volatile i32 %select, i32 addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_setcc_fneg_ule_posk_f32:
+; GCN: v_cmp_ngt_f32_e32 vcc, -4.0, v{{[0-9]+}}
+define void @test_setcc_fneg_ule_posk_f32() #0 {
+  %a = load volatile float, float addrspace(1)* undef
+  %x = load volatile i32, i32 addrspace(1)* undef
+  %y = load volatile i32, i32 addrspace(1)* undef
+  %neg.a = fsub float -0.0, %a
+  %cmp = fcmp ule float %neg.a, 4.0
+  %select = select i1 %cmp, i32 %x, i32 %y
+  store volatile i32 %select, i32 addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_setcc_fneg_une_posk_f32:
+; GCN: v_cmp_neq_f32_e32 vcc, -4.0, v{{[0-9]+}}
+define void @test_setcc_fneg_une_posk_f32() #0 {
+  %a = load volatile float, float addrspace(1)* undef
+  %x = load volatile i32, i32 addrspace(1)* undef
+  %y = load volatile i32, i32 addrspace(1)* undef
+  %neg.a = fsub float -0.0, %a
+  %cmp = fcmp une float %neg.a, 4.0
+  %select = select i1 %cmp, i32 %x, i32 %y
+  store volatile i32 %select, i32 addrspace(1)* undef
+  ret void
+}
+
+attributes #0 = { nounwind }

test/CodeGen/SystemZ/fp-cmp-05.ll

 ; Test that floating-point instructions that set cc are used to
 ; eliminate compares for load complement, load negative and load
 ; positive.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
 
 ; Load complement (sign-bit flipped).
 ; Test f32
 define float @f1(float %a, float %b, float %f) {
 ; CHECK-LABEL: f1:
-; CHECK: lcebr
+; CHECK: ltebr
 ; CHECK-NEXT: ber %r14
   %neg = fsub float -0.0, %f
   %cond = fcmp oeq float %neg, 0.0
   %res = select i1 %cond, float %a, float %b
   ret float %res
 }
 
 ; Test f64
 define double @f2(double %a, double %b, double %f) {
 ; CHECK-LABEL: f2:
-; CHECK: lcdbr
+; CHECK: ltdbr
 ; CHECK-NEXT: ber %r14
   %neg = fsub double -0.0, %f
   %cond = fcmp oeq double %neg, 0.0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Negation of floating-point absolute.
 ; Test f32
 declare float @llvm.fabs.f32(float %f)
 define float @f3(float %a, float %b, float %f) {
 ; CHECK-LABEL: f3:
-; CHECK: lnebr
+; CHECK: lpebr
 ; CHECK-NEXT: ber %r14
   %abs = call float @llvm.fabs.f32(float %f)
   %neg = fsub float -0.0, %abs
   %cond = fcmp oeq float %neg, 0.0
   %res = select i1 %cond, float %a, float %b
   ret float %res
 }
 
 ; Test f64
 declare double @llvm.fabs.f64(double %f)
 define double @f4(double %a, double %b, double %f) {
 ; CHECK-LABEL: f4:
-; CHECK: lndbr
+; CHECK: lpdbr
 ; CHECK-NEXT: ber %r14
   %abs = call double @llvm.fabs.f64(double %f)
   %neg = fsub double -0.0, %abs
   %cond = fcmp oeq double %neg, 0.0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 

test/CodeGen/XCore/fneg.ll

 ; RUN: llc < %s -march=xcore | FileCheck %s
-define i1 @test(double %F) nounwind {
+define i1 @test(double %F, double %G) nounwind {
 entry:
 ; CHECK-LABEL: test:
 ; CHECK: xor
   %0 = fsub double -0.000000e+00, %F
-  %1 = fcmp olt double 0.000000e+00, %0
+  %1 = fcmp olt double %G, %0
   ret i1 %1
 }