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[NVPTX] Implement min/max in tablegen, rather than with custom DAGComine logic.
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Authored by jlebar on Jan 14 2017, 8:55 AM.

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Summary

This change also lets us use max.{s,u}16. There's a vague warning in a
test about this maybe being less efficient, but I could not come up with
a case where the resulting SASS (sm_35 or sm_60) was different with or
without max.{s,u}16. It's true that nvcc seems to emit only
max.{s,u}32, but even ptxas 7.0 seems to have no problem generating
efficient SASS from max.{s,u}16 (the casts up to i32 and back down to
i16 seem to be implicit and nops, happening via register aliasing).

In the absence of evidence, better to have fewer special cases, emit
more straightforward code, etc. In particular, if a new GPU has 16-bit
min/max instructions, we want to be able to use them.

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rL LLVM

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jlebar updated this revision to Diff 84454.Jan 14 2017, 8:55 AM
jlebar retitled this revision from to [NVPTX] Implement min/max in tablegen, rather than with custom DAGComine logic..
jlebar updated this object.
jlebar added a reviewer: tra.
jlebar added a subscriber: llvm-commits.
tra accepted this revision.Jan 17 2017, 1:52 PM
This revision is now accepted and ready to land.Jan 17 2017, 1:52 PM
This revision was automatically updated to reflect the committed changes.