[NDS32 18/46] Add 32-bit Load/Store instructions with [Reg + Reg << Imm] addressing mode

[shiva0217]

Summary

Add 32-bit Load/Store instructions with [Reg + Reg << Imm] addressing mode

lib/Target/NDS32/InstPrinter/NDS32InstPrinter.h

public:
     static const char *getRegisterName(unsigned RegNo);
 
     void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
                       const char *Modifier = nullptr);
 
     void printRegName(raw_ostream &OS, unsigned RegNo) const override;
 
     void printAddrImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
+
+    void printAddrRegShift(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   };
 }
 
 #endif

lib/Target/NDS32/InstPrinter/NDS32InstPrinter.cpp

void NDS32InstPrinter::printAddrImmOperand(const MCInst *MI, unsigned OpNum,
 
   // Special value for #-0. All others are normal.
   if (OffImm == INT32_MIN)
     OffImm = 0;
 
   O << " + " << markup("<imm:") << "(" << formatImm(OffImm) << ")";
   O << markup(">") << "]" << markup(">");
 }
+
+// Print [Reg + Reg << Imm] addressing mode
+void NDS32InstPrinter::printAddrRegShift(const MCInst *MI, unsigned Op,
+                                         raw_ostream &O) {
+  const MCOperand &MO1 = MI->getOperand(Op);
+  const MCOperand &MO2 = MI->getOperand(Op + 1);
+  const MCOperand &MO3 = MI->getOperand(Op + 2);
+
+  O << markup("<mem:") << "[" << '$';
+  printRegName(O, MO1.getReg());
+  O << " + $";
+  printRegName(O, MO2.getReg());
+
+  int32_t Imm = (int32_t)MO3.getImm();
+  if (Imm) {
+    O << " << ";
+    O << MO3.getImm();
+  }
+  O << "]" << markup(">");
+}

lib/Target/NDS32/NDS32ISelDAGToDAG.cpp

namespace {
   bool SelectAddrImm15sHalf(SDValue Addr, SDValue &Base,
                             SDValue &Offset) const;
 
   // Select [Reg + Imm15s ] addressing mode for byte width load/store
   // instruction.
   bool SelectAddrImm15sByte(SDValue Addr, SDValue &Base,
                             SDValue &Offset) const;
 
-    // Include the pieces autogenerated from the target description.
+  // Select [Reg + Reg << imm] addressing mode
+  bool SelectLdStRegShift(SDValue N, SDValue &Base, SDValue &OffsetReg,
+                          SDValue &Shift);
+
   #include "NDS32GenDAGISel.inc"
 
   private:
     void Select(SDNode *N) override;
 
     // getImm - Return a target constant with the specified value.
     inline SDValue getImm(const SDNode *Node, uint64_t Imm) {
       return CurDAG->getTargetConstant(Imm, SDLoc(Node), Node->getValueType(0));
if ((Addr.getOpcode() == ISD::ADD
     return true;
 
   if (selectAddrFrameIndex(Addr, Base, Offset))
     return true;
 
   return false;
 }
 
+bool NDS32DAGToDAGISel::SelectLdStRegShift(SDValue N, SDValue &Base,
+                                           SDValue &OffsetReg,
+                                           SDValue &Shift) {
+  if (N.getOpcode() != ISD::ADD &&
+      // ISD::OR that is equivalent to an ISD::ADD.
+      !CurDAG->isBaseWithConstantOffset(N))
+    return false;
+
+  unsigned ShAmt = 0;
+
+  if (N.getOperand(1).getOpcode() == ISD::SHL) {
+    Base   = N.getOperand(0);
+
+    // Check to see if the RHS of the shift is a constant, if not, we can't fold
+    // it.
+    if (ConstantSDNode *Sh =
+           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
+      ShAmt = Sh->getZExtValue();
+      if (ShAmt < 4) {
+        OffsetReg = N.getOperand(1).getOperand(0);
+        Shift = CurDAG->getTargetConstant(ShAmt, SDLoc(N), MVT::i32);
+        return true;
+      } else {
+        return false;
+      }
+    }
+  // Try matching (R shl C) + (R).
+  } else if (N.getOpcode() != ISD::SUB && (N.getOperand(0).hasOneUse())) {
+    if (N.getOperand(0).getOpcode() == ISD::SHL) {
+      Base   = N.getOperand(1);
+      // Check to see if the RHS of the shift is a constant, if not, we can't
+      // fold it.
+      if (ConstantSDNode *Sh =
+          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
+        ShAmt = Sh->getZExtValue();
+        if (ShAmt < 4) {
+         OffsetReg = N.getOperand(0).getOperand(0);
+          Shift = CurDAG->getTargetConstant(ShAmt, SDLoc(N), MVT::i32);
+          return true;
+        } else {
+          ShAmt = 0;
+          return false;
+        }
+      }
+    }
+  }
+
+  // return [r + r] addressing mode
+  Base = N.getOperand(1);
+  OffsetReg = N.getOperand(0);
+  Shift = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
+
+  return true;
+}
+
 void NDS32DAGToDAGISel::Select(SDNode *Node) {
   SDLoc dl(Node);
 
   // Dump information about the Node being selected
   DEBUG(errs() << "Selecting: ");
   DEBUG(Node->dump(CurDAG));
   DEBUG(errs() << "\n");
 
   // If we have a custom node, we already have selected!
   if (Node->isMachineOpcode()) {
     DEBUG(errs() << "== ";
           Node->dump(CurDAG);
           errs() << "\n");
     Node->setNodeId(-1);
     return;
   }
 
   // Few custom selection stuff.
   switch (Node->getOpcode()) {
   default: break;
   case ISD::FrameIndex: {
-    break;
+    assert(Node->getValueType(0) == MVT::i32);
+    int FI = cast<FrameIndexSDNode>(Node)->getIndex();
+    SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);
+    if (Node->hasOneUse()) {
+      CurDAG->SelectNodeTo(Node, NDS32::ADDI, MVT::i32, TFI,
+                           CurDAG->getTargetConstant(0, dl, MVT::i32));
+      return;
+    }
+    ReplaceNode(Node, CurDAG->getMachineNode(
+                          NDS32::ADDI, dl, MVT::i32, TFI,
+                          CurDAG->getTargetConstant(0, dl, MVT::i32)));
+    return;
   }
   case ISD::LOAD:
     break;
   case ISD::STORE:
     break;
   case ISD::ADD:
     // Other cases are autogenerated.
     break;

lib/Target/NDS32/NDS32InstrFormats.td

  
 class SHIForm<dag outs, dag ins, string asmstr, list<dag> pattern>
   : 32Bit_5R20Addr<0b001001, outs, ins, asmstr, pattern>;
 
 class SBIForm<dag outs, dag ins, string asmstr, list<dag> pattern>
   : 32Bit_5R20Addr<0b001000, outs, ins, asmstr, pattern>;
  
 
+class MEMForm<dag outs, dag ins, string asmstr, list<dag> pattern,
+              bits<8> subop_encode>
+  : 32BitInst<0b011100, outs, ins, asmstr, pattern> {
+  bits<5>  Rt;
+  bits<12> addr;
+  let Inst{24-20} = Rt;
+  let Inst{19-15} = addr{11-7}; // Ra
+  let Inst{14-10} = addr{6-2};  // Rb
+  let Inst{9-8} = addr{1-0};    // sv
+  let Inst{7-0} = subop_encode;
+}
+
+
 class JREGForm<dag outs, dag ins, string asmstr, list<dag> pattern>
   : 32BitInst<0b100101, outs, ins, asmstr, pattern>;
 
 // Pseudo instructions
 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
   : 32BitInst<0b110010, outs, ins, asmstr, pattern> {
   let Inst{15-0} = 0;
   let Pattern = pattern;
   let isCodeGenOnly = 1;
   let isPseudo = 1;
 }

lib/Target/NDS32/NDS32InstrInfo.td

def SHI: SHIForm<(outs), (ins GPR:$Rt, addr_imm15s_half:$addr),
                  [(truncstorei16 GPR:$Rt, addr_imm15s_half:$addr)]>;
 
 def SBI: SBIForm<(outs), (ins GPR:$Rt, addr_imm15s_byte:$addr),
                  "sbi\t$Rt, $addr",
                  [(truncstorei8 GPR:$Rt, addr_imm15s_byte:$addr)]>;
 }
  
 
+let mayLoad = 1 in
+class MEM_load<string opstr, SDPatternOperator Op, bits<8> subop_encode> :
+  MEMForm<(outs GPR:$Rt), (ins ldst_reg_shift:$addr),
+          !strconcat(opstr, "\t$Rt, $addr"),
+          [(set GPR:$Rt, (Op ldst_reg_shift:$addr))], subop_encode>;
+
+def LW     : MEM_load< "lw",    load,        0b00000010>;
+def LH     : MEM_load< "lh",    zextloadi16, 0b00000001>;
+def LHS    : MEM_load< "lhs",   sextloadi16, 0b00010001>;
+def LB     : MEM_load< "lb",    zextloadi8,  0b00000000>;
+def LBS    : MEM_load< "lbs",   sextloadi8,  0b00010000>;
+
+
+let mayStore = 1 in
+class MEM_store<string opstr, SDPatternOperator Op, bits<8> subop_encode> :
+  MEMForm<(outs), (ins GPR:$Rt, ldst_reg_shift:$addr),
+          !strconcat(opstr, "\t$Rt, $addr"),
+          [(Op GPR:$Rt, ldst_reg_shift:$addr)], subop_encode>;
+
+def SW     : MEM_store< "sw",    store,         0b00001010>;
+def SH     : MEM_store< "sh",    truncstorei16, 0b00001001>;
+def SB     : MEM_store< "sb",    truncstorei8,  0b00001000>;
+
+
 class JREG_ret<string opstr, list<dag> pat, bits<2> dt_it> :
   JREGForm<(outs), (ins), opstr, pat> {
   let Inst{24-15} = 0;
   let Inst{14-10} = 30;  // LP register number
   let Inst{9-8} = dt_it; // DT/IT
   let Inst{7-6} = 0;
   let Inst{5} = 1;
   let Inst{4-0} = 0;

lib/Target/NDS32/NDS32Predicate.td

 def addr_imm15s_byte : MemOperand,
     ComplexPattern<i32, 2, "SelectAddrImm15sByte", []> {
   // 15-bit signed immediate operand. Note that for word size load/store
   // immediate access range would be +/- (imm15s).
 
   let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
   let PrintMethod = "printAddrImmOperand";
 }
+
+// ldst_reg_shift := [reg + reg << sv]
+// sv: shift value could be 0, 1, 2, 3
+def MemAddrRegShiftAsmOperand : AsmOperandClass { let Name = "AddrRegShift"; }
+def ldst_reg_shift : MemOperand,
+                  ComplexPattern<i32, 3, "SelectLdStRegShift", []> {
+  let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$shift);
+  let PrintMethod = "printAddrRegShift";
+}

test/CodeGen/NDS32/load-store-insns.ll

 entry:
   %a.addr = alloca i8, align 1
   store i8 %a, i8* %a.addr, align 1
   %0 = load i8, i8* %a.addr, align 1
 ; CHECK: sbi     $r0, [$sp + (7)]
 ; CHECK: lbi     $r0, [$sp + (7)]
   ret i8 %0
 }
+
+; Function Attrs: noinline nounwind
+define i32 @sw_lwi_lw(i32 %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  %b = alloca [100000 x i32], align 4
+  store i32 %a, i32* %a.addr, align 4
+  %arrayidx = getelementptr inbounds [100000 x i32], [100000 x i32]* %b, i32 0, i32 9999
+  store i32 3, i32* %arrayidx, align 4
+  %0 = load i32, i32* %a.addr, align 4
+  %arrayidx1 = getelementptr inbounds [100000 x i32], [100000 x i32]* %b, i32 0, i32 %0
+  %1 = load i32, i32* %arrayidx1, align 4
+; CHECK: sw      $r2, [$r1 + $r0]
+; CHECK: lwi     $r1, [$sp + (400004)]
+; CHECK: lw      $r0, [$r0 + $r1 << 2]
+  ret i32 %1
+}
+
+; Function Attrs: noinline nounwind
+define signext i16 @sh_lhs(i32 %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  %b = alloca [100000 x i16], align 2
+  store i32 %a, i32* %a.addr, align 4
+  %arrayidx = getelementptr inbounds [100000 x i16], [100000 x i16]* %b, i32 0, i32 9999
+  store i16 3, i16* %arrayidx, align 2
+  %0 = load i32, i32* %a.addr, align 4
+  %arrayidx1 = getelementptr inbounds [100000 x i16], [100000 x i16]* %b, i32 0, i32 %0
+  %1 = load i16, i16* %arrayidx1, align 2
+; CHECK: sh      $r2, [$r1 + $r0]
+; CHECK: lhs     $r0, [$r0 + $r1 << 1]
+  ret i16 %1
+}
+
+; Function Attrs: noinline nounwind
+define zeroext i16 @sh_lh(i32 %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  %b = alloca [100000 x i16], align 2
+  store i32 %a, i32* %a.addr, align 4
+  %arrayidx = getelementptr inbounds [100000 x i16], [100000 x i16]* %b, i32 0, i32 9999
+  store i16 3, i16* %arrayidx, align 2
+  %0 = load i32, i32* %a.addr, align 4
+  %arrayidx1 = getelementptr inbounds [100000 x i16], [100000 x i16]* %b, i32 0, i32 %0
+  %1 = load i16, i16* %arrayidx1, align 2
+; CHECK: sh      $r2, [$r1 + $r0]
+; CHECK: lh      $r0, [$r0 + $r1 << 1]
+  ret i16 %1
+}
+
+; Function Attrs: noinline nounwind
+define signext i8 @sb_lbs(i32 %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  %b = alloca [100000 x i8], align 1
+  store i32 %a, i32* %a.addr, align 4
+  %arrayidx = getelementptr inbounds [100000 x i8], [100000 x i8]* %b, i32 0, i32 9999
+  store i8 3, i8* %arrayidx, align 1
+  %0 = load i32, i32* %a.addr, align 4
+  %arrayidx1 = getelementptr inbounds [100000 x i8], [100000 x i8]* %b, i32 0, i32 %0
+  %1 = load i8, i8* %arrayidx1, align 1
+; CHECK: sb      $r2, [$r1 + $r0]
+; CHECK: lbs     $r0, [$r1 + $r0]
+  ret i8 %1
+}
+
+; Function Attrs: noinline nounwind
+define zeroext i8 @sb_lb(i32 %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  %b = alloca [100000 x i8], align 1
+  store i32 %a, i32* %a.addr, align 4
+  %arrayidx = getelementptr inbounds [100000 x i8], [100000 x i8]* %b, i32 0, i32 9999
+  store i8 3, i8* %arrayidx, align 1
+  %0 = load i32, i32* %a.addr, align 4
+  %arrayidx1 = getelementptr inbounds [100000 x i8], [100000 x i8]* %b, i32 0, i32 %0
+  %1 = load i8, i8* %arrayidx1, align 1
+; CHECK: sb      $r2, [$r1 + $r0]
+; CHECK: lb      $r0, [$r1 + $r0]
+  ret i8 %1
+}