[NDS32 16/46] Add Move Immediate value Instructions

[shiva0217]

Summary

Add Move Immediate value Instructions

lib/Target/NDS32/NDS32InstrFormats.td

class 32BitInst<bits<6> opcode,
   field bits<32> Inst;
   let Size = 4;
 
   let Pattern = pattern;
   let Inst{31} = 0;
   let Inst{30-25} = opcode;
 }
 
+class SETHIForm<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 32BitInst<0b100011, outs, ins, asmstr, pattern> {
+  bits<5> Rt;
+  bits<20> imm;
+  let Inst{24-20} = Rt;
+  let Inst{19-0} = imm;
+}
+
+class MOVIForm<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 32BitInst<0b100010, outs, ins, asmstr, pattern> {
+  bits<5> Rt;
+  bits<20> imm;
+  let Inst{24-20} = Rt;
+  let Inst{19-0} = imm;
+}
+
 class ALU_1Form<dag outs, dag ins, string asmstr, list<dag> pattern>
   : 32BitInst<0b100000, outs, ins, asmstr, pattern>;
 
 class ALU_2Form_rr<dag outs, dag ins, string asmstr, list<dag> pattern,
                    bits<6> sub_opcode>
   : 32BitInst<0b100001, outs, ins, asmstr, pattern> {
   bits<5> Rt;
   bits<5> Ra;

lib/Target/NDS32/NDS32InstrInfo.td

def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
                               [(NDS32callseq_start timm:$amt)]>;
 def ADJCALLSTACKUP   : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
                               "#ADJCALLSTACKUP",
                               [(NDS32callseq_end timm:$amt1, timm:$amt2)]>;
 }
 
 
 //===----------------------------------------------------------------------===//
+// Move Instructions
+//
+
+def SETHI : SETHIForm<(outs GPR:$Rt), (ins imm20u:$imm),
+                      "sethi\t$Rt, $imm", []>;
+
+let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
+def MOVI : MOVIForm<(outs GPR:$Rt), (ins imm20s:$imm),
+                    "movi\t$Rt, $imm",
+                    [(set GPR:$Rt, (imm20s:$imm))]>;
+
+
+//===----------------------------------------------------------------------===//
 // Arithmetic Instructions
 //
 
 class ALU_1_rr<string opstr, SDPatternOperator Op, bits<5> subop_encode> :
   ALU_1Form<(outs GPR:$Rt), (ins GPR:$Ra, GPR:$Rb),
             !strconcat(opstr, "\t$Rt, $Ra, $Rb"),
             [(set GPR:$Rt, (Op GPR:$Ra, GPR:$Rb))]> {
   bits<5> Rt;
let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
   def RET  : JREG_ret<"ret", [(NDS32ret)], 0b00>;
 }
 
 
 //===----------------------------------------------------------------------===//
 // Pattern Transformation
 //===----------------------------------------------------------------------===//
 
+// Arbitrary immediates
+def : Pat<(i32 imm:$imm),
+          (ORI (SETHI (HI20 imm:$imm)), (LO12 imm:$imm))>;
+
 // division patterns
 def : Pat<(NDS32sdivrem i32:$Ra, i32:$Rb),
           (SDIVREM i32:$Ra, i32:$Rb)>;
 def : Pat<(NDS32udivrem i32:$Ra, i32:$Rb),
           (UDIVREM i32:$Ra, i32:$Rb)>;
-

lib/Target/NDS32/NDS32Predicate.td

 // This file describes the NDS32 Predicate defs in TableGen format.
 //
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // Immediate Operand Predicates
 //
 
+// Transformation Function - get the lower 12 bits.
+def LO12 : SDNodeXForm<imm, [{
+  return getImm(N, N->getZExtValue() & 0xFFF);
+}]>;
+
+// Transformation Function - get the higher 20 bits.
+def HI20 : SDNodeXForm<imm, [{
+  return getImm(N, (N->getZExtValue() >> 12) & 0xFFFFF);
+}]>;
+
 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
 
 /// imm15s predicate - Immediate in the range [-(1 << 14) , (1 << 14)].
 def Imm15sAsmOperand: ImmAsmOperand {
   let Name = "Imm15s";
   let DiagnosticType = "ImmRange15s";
 }
 def imm15s : Operand<i32>, ImmLeaf<i32, [{
def Imm15uAsmOperand: ImmAsmOperand {
   let Name = "Imm15u";
   let DiagnosticType = "ImmRange15u";
 }
 def imm15u : Operand<i32>, ImmLeaf<i32, [{
   return Imm >= 0 && Imm < (1 << 15);
 }]> {
 }
 
+/// imm20u predicate - Immediate in the range [0 , (1 << 20)].
+def Imm20uAsmOperand: ImmAsmOperand {
+  let Name = "Imm20u";
+  let DiagnosticType = "ImmRange20u";
+}
+def imm20u : Operand<i32>, ImmLeaf<i32, [{
+  return Imm >= 0 && Imm < (1 << 20);
+}]> {
+}
+
 
 //===----------------------------------------------------------------------===//
 // Load/Store Operands Predicates
 //
 
 class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; }
 
 // addr_imm15s_word := [reg + imm15s << 2]

test/CodeGen/NDS32/move-imm.ll

+; RUN: llc < %s | FileCheck %s
+target datalayout = "e-m:e-p:32:32-i64:64-a:0:32-n32-S64"
+target triple = "nds32le---elf"
+
+; Function Attrs: noinline nounwind
+define i32 @movi() #0 {
+entry:
+  ret i32 123456
+; CHECK: movi    $r0, 123456
+}
+
+; Function Attrs: noinline nounwind
+define i32 @sethi_ori() #0 {
+entry:
+  ret i32 1234567
+; CHECK: sethi   $r0, 301
+; CHECK: ori     $r0, $r0, 1671
+}