[NDS32 10/46] Add preliminary NDS32 Calling Convention

[shiva0217]

Summary

Add preliminary NDS32 Calling Convention

lib/Target/NDS32/CMakeLists.txt

 set(LLVM_TARGET_DEFINITIONS NDS32.td)
 
 tablegen(LLVM NDS32GenSubtargetInfo.inc -gen-subtarget)
 tablegen(LLVM NDS32GenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM NDS32GenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM NDS32GenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM NDS32GenCallingConv.inc -gen-callingconv)
 
 add_public_tablegen_target(NDS32CommonTableGen)
 
 
 add_llvm_target(NDS32CodeGen
   NDS32TargetMachine.cpp
   NDS32Subtarget.cpp
   NDS32FrameLowering.cpp
   NDS32RegisterInfo.cpp
   NDS32InstrInfo.cpp
   NDS32ISelDAGToDAG.cpp
   NDS32ISelLowering.cpp
+  NDS32MachineFunctionInfo.cpp
   )
 
 add_subdirectory(TargetInfo)
 add_subdirectory(MCTargetDesc)

lib/Target/NDS32/NDS32.td

 
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
 
 include "NDS32RegisterInfo.td"
 
 //===----------------------------------------------------------------------===//
+// Calling Convention Description
+//===----------------------------------------------------------------------===//
+
+include "NDS32CallingConv.td"
+
+//===----------------------------------------------------------------------===//
 // Instruction Descriptions
 //===----------------------------------------------------------------------===//
 
 include "NDS32InstrInfo.td"
 
 def NDS32InstrInfo : InstrInfo;
 
 //===----------------------------------------------------------------------===//
 // Target Declaration
 //===----------------------------------------------------------------------===//
 
 def NDS32 : Target {
   let InstructionSet = NDS32InstrInfo;
 }

lib/Target/NDS32/NDS32CallingConv.td

+//==- NDS32CallingConv.td - Calling Conventions for NDS32 -*- tablegen -*---==//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+// This describes the calling conventions for NDS32 architecture.
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// NDS32 Return Value Calling Convention
+//===----------------------------------------------------------------------===//
+def RetCC_NDS32_SoftFloat : CallingConv<[
+  CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
+  CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
+  CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>,
+
+  CCIfType<[f32], CCBitConvertToType<i32>>
+]>;
+
+def RetCC_NDS32 : CallingConv<[
+  CCDelegateTo<RetCC_NDS32_SoftFloat>
+]>;
+
+//===----------------------------------------------------------------------===//
+// NDS32 Argument Calling Conventions
+//===----------------------------------------------------------------------===//
+
+/// CCIfAlign - Match of the original alignment of the arg
+class CCIfAlign<string Align, CCAction A>:
+  CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
+
+class CCIfNotAlign<string Align, CCAction A>:
+  CCIf<!strconcat("ArgFlags.getOrigAlign() != ", Align), A>;
+
+def CC_NDS32_SoftFloat : CallingConv<[
+  CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
+
+  // Pass by value if the byval attribute is given
+  CCIfByVal<CCPassByVal<4, 4>>,
+
+  // The first to sixth argument are passed with register R0 ~ R5.
+  // Not align to 8 byte mean it's i32 or f32
+  CCIfType<[i32], CCIfNotAlign<"8", CCAssignToReg<[R0, R1, R2, R3, R4, R5]>>>,
+  // Align to 8 byte mean it's i64 or f64, it's passed in even pairs of GPRs
+  // need to pad R1/R3 if assign to R2/R4.
+  CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2, R4],
+                                                         [R0, R1, R3]>>>,
+
+  // If a part of argument assign to stack, shadow the argument registers.
+  // To avoid a double argument assign to stack and register in the same time.
+  CCIfType<[i32], CCIfAlign<"8", CCAssignToStackWithShadow<4, 8, [R0, R1, R2,
+                                                                  R3, R4, R5]>>>,
+
+  CCIfType<[f32], CCBitConvertToType<i32>>,
+  CCIfType<[i64, f64], CCAssignToRegWithShadow<[R0, R2, R4], [R1, R3, R5]>>,
+
+  CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
+  CCIfType<[i64, f64], CCAssignToStack<8, 8>>
+]>;
+
+def CC_NDS32 : CallingConv<[
+  CCDelegateTo<CC_NDS32_SoftFloat>
+]>;
+
+
+//===----------------------------------------------------------------------===//
+// Callee-saved register lists.
+//===----------------------------------------------------------------------===//
+
+// Callee save registers for V3 Architecture
+def CSR_V3 : CalleeSavedRegs<(add LP, FP, (sequence "R%u", 14, 6))>;

lib/Target/NDS32/NDS32ISelLowering.h

private:
     SDValue
     LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
                          const SmallVectorImpl<ISD::InputArg> &Ins,
                          const SDLoc &dl, SelectionDAG &DAG,
                          SmallVectorImpl<SDValue> &InVals) const override;
     SDValue
       LowerCall(TargetLowering::CallLoweringInfo &CLI,
                 SmallVectorImpl<SDValue> &InVals) const override;
+
+    SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
+                        const SmallVectorImpl<ISD::OutputArg> &Outs,
+                        const SmallVectorImpl<SDValue> &OutVals,
+                        const SDLoc &dl, SelectionDAG &DAG) const override;
   };
 } // namespace llvm
 
 #endif

lib/Target/NDS32/NDS32ISelLowering.cpp

 // This file implements the NDS32TargetLowering class.
 //
 //===----------------------------------------------------------------------===//
 
 #include "NDS32ISelLowering.h"
 #include "NDS32.h"
 #include "NDS32Subtarget.h"
 #include "NDS32TargetMachine.h"
+#include "NDS32MachineFunctionInfo.h"
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
 #include "llvm/CodeGen/ValueTypes.h"
NDS32TargetLowering::getRegForInlineAsmConstraint(
 
   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
 }
 
 //===----------------------------------------------------------------------===//
 //                      Calling Convention Implementation
 //===----------------------------------------------------------------------===//
 
+#include "NDS32GenCallingConv.inc"
+
+// addLiveIn - This helper function adds the specified physical register to the
+// MachineFunction as a live in value.  It also creates a corresponding
+// virtual register for it.
+static unsigned
+addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
+{
+  unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
+  MF.getRegInfo().addLiveIn(PReg, VReg);
+  return VReg;
+}
+
+static const MCPhysReg NDS32ArgRegs[6] = {
+    NDS32::R0, NDS32::R1, NDS32::R2,
+    NDS32::R3, NDS32::R4, NDS32::R5
+};
+
 // LowerFormalArguments - Specify how callee get arguments
 SDValue NDS32TargetLowering::LowerFormalArguments(
     SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
+  MachineFunction &MF = DAG.getMachineFunction();
+  MachineFrameInfo &MFI = MF.getFrameInfo();
+  NDS32MachineFunctionInfo *FI = MF.getInfo<NDS32MachineFunctionInfo>();
+
+  FI->setVarArgsFrameIndex(0);
+
+  // Used with vargs to accumulate store chains.
+  std::vector<SDValue> OutChains;
+
+  // Assign locations to all of the incoming arguments.
+  SmallVector<CCValAssign, 16> ArgLocs;
+
+  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
+                 *DAG.getContext());
+
+  const Function *Func = DAG.getMachineFunction().getFunction();
+  Function::const_arg_iterator FuncArg = Func->arg_begin();
+
+  CCInfo.AnalyzeFormalArguments(Ins, CC_NDS32_SoftFloat);
+
+  unsigned CurArgIdx = 0;
+
+  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
+    CCValAssign &VA = ArgLocs[i];
+    if (Ins[i].isOrigArg()) {
+      std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx);
+      CurArgIdx = Ins[i].getOrigArgIndex();
+    }
+    ISD::ArgFlagsTy Flags = Ins[i].Flags;
+    bool IsRegLoc = VA.isRegLoc();
+    // Arguments stored on registers
+    if (IsRegLoc) {
+      MVT RegVT = VA.getLocVT();
+      unsigned ArgReg = VA.getLocReg();
+      const TargetRegisterClass *RC = getRegClassFor(RegVT);
+
+      // Transform the arguments stored on
+      // physical registers into virtual ones
+      unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
+      SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
+
+      InVals.push_back(ArgValue);
+    } else { // VA.isRegLoc()
+      MVT LocVT = VA.getLocVT();
+
+      // sanity check
+      assert(VA.isMemLoc());
+
+      // The stack pointer offset is relative to the caller stack frame.
+      int FrameIdx = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
+                                      VA.getLocMemOffset(), true);
+      // Create load nodes to retrieve arguments from the stack
+      SDValue FIN = DAG.getFrameIndex(FrameIdx,
+                                      getPointerTy(DAG.getDataLayout()));
+      SDValue ArgValue = DAG.getLoad(
+          LocVT, DL, Chain, FIN,
+          MachinePointerInfo::getFixedStack(DAG.getMachineFunction(),
+                                            FrameIdx));
+      OutChains.push_back(ArgValue.getValue(1));
+
+      InVals.push_back(ArgValue);
+    }
+  }
+
+  // All stores are grouped in one node to allow the matching between
+  // the size of Ins and InVals. This only happens when on varg functions
+  if (!OutChains.empty()) {
+    OutChains.push_back(Chain);
+    Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
+  }
 
   return Chain;
 }
 
+// LowerReturn - Specify how callee return value
+SDValue
+NDS32TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
+                                 bool isVarArg,
+                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
+                                 const SmallVectorImpl<SDValue> &OutVals,
+                                 const SDLoc &dl, SelectionDAG &DAG) const {
+
+  // CCValAssign - represent the assignment of the return value to a location
+  SmallVector<CCValAssign, 16> RVLocs;
+
+  // CCState - Info about the registers and stack slot.
+  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
+                 *DAG.getContext());
+
+  // Analize return values.
+  CCInfo.AnalyzeReturn(Outs, RetCC_NDS32);
+
+  SDValue Flag;
+  SmallVector<SDValue, 4> RetOps(1, Chain);
+
+  // Copy the result values into the output registers.
+  for (unsigned i = 0; i != RVLocs.size(); ++i) {
+    CCValAssign &VA = RVLocs[i];
+    assert(VA.isRegLoc() && "Can only return in registers!");
+
+    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
+                             OutVals[i], Flag);
+
+    // Guarantee that all emitted copies are stuck together,
+    // avoiding something bad.
+    Flag = Chain.getValue(1);
+    RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
+  }
+
+  unsigned Opc = NDS32ISD::RET;
+
+  RetOps[0] = Chain;  // Update chain.
+
+  // Add the flag if we have it.
+  if (Flag.getNode())
+    RetOps.push_back(Flag);
+
+  return DAG.getNode(Opc, dl, MVT::Other, RetOps);
+}
+
 // LowerCall - Specify how caller passing arguments
 SDValue
 NDS32TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
                                SmallVectorImpl<SDValue> &InVals) const {
   SDValue Chain;
   return Chain;
 }
 

lib/Target/NDS32/NDS32InstrFormats.td

class 32BitInst<bits<6> opcode,
   field bits<32> Inst;
   let Size = 4;
 
   let Pattern = pattern;
   let Inst{31} = 0;
   let Inst{30-25} = opcode;
 }
 
+class JREGForm<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 32BitInst<0b100101, outs, ins, asmstr, pattern>;
+
 // Pseudo instructions
 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
   : 32BitInst<0b110010, outs, ins, asmstr, pattern> {
   let Inst{15-0} = 0;
   let Pattern = pattern;
   let isCodeGenOnly = 1;
   let isPseudo = 1;
 }

lib/Target/NDS32/NDS32InstrInfo.td

 // Type Profiles.
 //===----------------------------------------------------------------------===//
 def SDT_NDS32CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
 def SDT_NDS32CallSeqEnd   : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
 
 //===----------------------------------------------------------------------===//
 // NDS32 Specific Node Definitions.
 //===----------------------------------------------------------------------===//
+def NDS32ret     : SDNode<"NDS32ISD::RET", SDTNone,
+                       [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
 def NDS32callseq_start :
                  SDNode<"ISD::CALLSEQ_START", SDT_NDS32CallSeqStart,
                         [SDNPHasChain, SDNPOutGlue]>;
 def NDS32callseq_end :
                  SDNode<"ISD::CALLSEQ_END",   SDT_NDS32CallSeqEnd,
                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 
 //===----------------------------------------------------------------------===//
 // ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into
 // a stack adjustment and the codegen must know that they may modify the stack
 // pointer before prolog-epilog rewriting occurs.
 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
 // sub / add.
 let Defs = [SP], Uses = [SP] in {
 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
                               "#ADJCALLSTACKDOWN",
                               [(NDS32callseq_start timm:$amt)]>;
 def ADJCALLSTACKUP   : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
                               "#ADJCALLSTACKUP",
                               [(NDS32callseq_end timm:$amt1, timm:$amt2)]>;
 }
+
+class JREG_ret<string opstr, list<dag> pat, bits<2> dt_it> :
+  JREGForm<(outs), (ins), opstr, pat> {
+  let Inst{24-15} = 0;
+  let Inst{14-10} = 30;  // LP register number
+  let Inst{9-8} = dt_it; // DT/IT
+  let Inst{7-6} = 0;
+  let Inst{5} = 1;
+  let Inst{4-0} = 0;
+}
+
+let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
+  def RET  : JREG_ret<"ret", [(NDS32ret)], 0b00>;
+}

lib/Target/NDS32/NDS32MachineFunctionInfo.h

+//=== NDS32MachineFunctionInfo.h - NDS32 machine function info -*- C++ -*---==//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares NDS32-specific per-machine-function information.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_NDS32_NDS32MACHINEFUNCTIONINFO_H
+#define LLVM_LIB_TARGET_NDS32_NDS32MACHINEFUNCTIONINFO_H
+
+#include "llvm/CodeGen/MachineFunction.h"
+
+namespace llvm {
+
+/// NDS32MachineFunctionInfo - This class is derived from MachineFunction and
+/// contains private NDS32 target-specific information for each MachineFunction.
+class NDS32MachineFunctionInfo : public MachineFunctionInfo {
+  virtual void anchor();
+
+  /// CalleeSavedFrameSize - Size of the callee-saved register portion of the
+  /// stack frame in bytes.
+  unsigned CalleeSavedFrameSize;
+
+  /// ReturnAddrIndex - FrameIndex for return slot.
+  int ReturnAddrIndex;
+
+  /// VarArgsFrameIndex - FrameIndex for start of varargs area.
+  int VarArgsFrameIndex;
+
+public:
+  NDS32MachineFunctionInfo() : CalleeSavedFrameSize(0) {}
+
+  explicit NDS32MachineFunctionInfo(MachineFunction &MF)
+    : CalleeSavedFrameSize(0), ReturnAddrIndex(0) {}
+
+  unsigned getCalleeSavedFrameSize() const { return CalleeSavedFrameSize; }
+  void setCalleeSavedFrameSize(unsigned bytes) { CalleeSavedFrameSize = bytes; }
+
+  int getRAIndex() const { return ReturnAddrIndex; }
+  void setRAIndex(int Index) { ReturnAddrIndex = Index; }
+
+  int getVarArgsFrameIndex() const { return VarArgsFrameIndex;}
+  void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
+};
+
+} // End llvm namespace
+
+#endif

lib/Target/NDS32/NDS32MachineFunctionInfo.cpp

+//===-- NDS32MachineFunctionInfo.cpp - NDS32 machine function info --------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "NDS32MachineFunctionInfo.h"
+
+using namespace llvm;
+
+void NDS32MachineFunctionInfo::anchor() { }

lib/Target/NDS32/NDS32RegisterInfo.cpp

 #include "NDS32GenRegisterInfo.inc"
 
 NDS32RegisterInfo::NDS32RegisterInfo()
   : NDS32GenRegisterInfo(NDS32::LP) {}
 
 const MCPhysReg*
 NDS32RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
 
-  return nullptr;
+  return CSR_V3_SaveList;
 }
 
 const uint32_t *
 NDS32RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
                                         CallingConv::ID) const {
-  return nullptr;
+  return CSR_V3_RegMask;
 }
 
 BitVector NDS32RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   BitVector Reserved(getNumRegs());
   const NDS32FrameLowering *TFI = getFrameLowering(MF);
 
   Reserved.set(NDS32::R15);
   Reserved.set(NDS32::R26);