[NDS32 6/46] Add preliminary NDS32 RegisterInfo class

[shiva0217]

Summary

Add preliminary NDS32 RegisterInfo class

[shiva0217]

This comment was removed by shiva0217.

lib/Target/NDS32/CMakeLists.txt

 set(LLVM_TARGET_DEFINITIONS NDS32.td)
 
 tablegen(LLVM NDS32GenSubtargetInfo.inc -gen-subtarget)
+tablegen(LLVM NDS32GenRegisterInfo.inc -gen-register-info)
 
 add_public_tablegen_target(NDS32CommonTableGen)
 
 
 add_llvm_target(NDS32CodeGen
   NDS32TargetMachine.cpp
   NDS32Subtarget.cpp
   NDS32FrameLowering.cpp
+  NDS32RegisterInfo.cpp
   )
 
 add_subdirectory(TargetInfo)
 add_subdirectory(MCTargetDesc)

lib/Target/NDS32/MCTargetDesc/NDS32MCTargetDesc.h

 class raw_pwrite_stream;
 
 Target &getTheNDS32Target();
 
 } // End llvm namespace
 
 #define GET_SUBTARGETINFO_ENUM
 #include "NDS32GenSubtargetInfo.inc"
-
+// Defines symbolic names for NDS32 registers.
+// This defines a mapping from register name to register number.
+#define GET_REGINFO_ENUM
+#include "NDS32GenRegisterInfo.inc"
 
 #endif

lib/Target/NDS32/MCTargetDesc/NDS32MCTargetDesc.cpp

 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_SUBTARGETINFO_MC_DESC
 #include "NDS32GenSubtargetInfo.inc"
 
+#define GET_REGINFO_MC_DESC
+#include "NDS32GenRegisterInfo.inc"
+
 static MCSubtargetInfo *
 createNDS32MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
   return createNDS32MCSubtargetInfoImpl(TT, CPU, FS);
 }
 
+static MCRegisterInfo *createNDS32MCRegisterInfo(const Triple &TT) {
+  MCRegisterInfo *X = new MCRegisterInfo();
+  InitNDS32MCRegisterInfo(X, NDS32::LP);
+  return X;
+}
+
 extern "C" void LLVMInitializeNDS32TargetMC() {
   // Register the MC subtarget info.
   TargetRegistry::RegisterMCSubtargetInfo(getTheNDS32Target(),
                                           createNDS32MCSubtargetInfo);
+
+  // Register the MC register info.
+  TargetRegistry::RegisterMCRegInfo(getTheNDS32Target(),
+                                    createNDS32MCRegisterInfo);
 }

lib/Target/NDS32/NDS32.td

 // NDS32 supported processors.
 //===----------------------------------------------------------------------===//
 class Proc<string Name, list<SubtargetFeature> Features>
  : Processor<Name, NoItineraries, Features>;
 
 def : Proc<"generic",         []>;
 
 //===----------------------------------------------------------------------===//
+// Register File Description
+//===----------------------------------------------------------------------===//
+
+include "NDS32RegisterInfo.td"
+
+//===----------------------------------------------------------------------===//
 // Target Declaration
 //===----------------------------------------------------------------------===//
 
 def NDS32 : Target {
 }

lib/Target/NDS32/NDS32RegisterInfo.h

+//===-- NDS32RegisterInfo.h - NDS32 Register Information Impl -*- C++ -*---===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the NDS32 implementation of the MRegisterInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_NDS32_NDS32REGISTERINFO_H
+#define LLVM_LIB_TARGET_NDS32_NDS32REGISTERINFO_H
+
+#include "llvm/Target/TargetRegisterInfo.h"
+
+#define GET_REGINFO_HEADER
+#include "NDS32GenRegisterInfo.inc"
+
+namespace llvm {
+
+struct NDS32RegisterInfo : public NDS32GenRegisterInfo {
+public:
+  NDS32RegisterInfo();
+
+  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
+  const uint32_t *getCallPreservedMask(const MachineFunction &MF,
+                                       CallingConv::ID) const override;
+
+  BitVector getReservedRegs(const MachineFunction &MF) const override;
+  const TargetRegisterClass*
+  getPointerRegClass(const MachineFunction &MF,
+                     unsigned Kind = 0) const override;
+
+  void eliminateFrameIndex(MachineBasicBlock::iterator II,
+                           int SPAdj, unsigned FIOperandNum,
+                           RegScavenger *RS = nullptr) const override;
+
+  // Debug information queries.
+  unsigned getFrameRegister(const MachineFunction &MF) const override;
+};
+
+} // end namespace llvm
+
+#endif

lib/Target/NDS32/NDS32RegisterInfo.cpp

+//===-- NDS32RegisterInfo.cpp - NDS32 Register Information ----------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the NDS32 implementation of the TargetRegisterInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "NDS32RegisterInfo.h"
+#include "NDS32.h"
+#include "NDS32TargetMachine.h"
+#include "llvm/ADT/BitVector.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/IR/Function.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetOptions.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "NDS32-reg-info"
+
+#define GET_REGINFO_TARGET_DESC
+#include "NDS32GenRegisterInfo.inc"
+
+NDS32RegisterInfo::NDS32RegisterInfo()
+  : NDS32GenRegisterInfo(NDS32::LP) {}
+
+const MCPhysReg*
+NDS32RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
+
+  return nullptr;
+}
+
+const uint32_t *
+NDS32RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
+                                        CallingConv::ID) const {
+  return nullptr;
+}
+
+BitVector NDS32RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
+  BitVector Reserved(getNumRegs());
+  const NDS32FrameLowering *TFI = getFrameLowering(MF);
+
+  Reserved.set(NDS32::R15);
+  Reserved.set(NDS32::R26);
+  Reserved.set(NDS32::R27);
+
+  Reserved.set(NDS32::GP);
+  Reserved.set(NDS32::LP);
+  Reserved.set(NDS32::SP);
+  // Mark frame pointer as reserved if needed.
+  if (TFI->hasFP(MF))
+    Reserved.set(NDS32::FP);
+
+  return Reserved;
+}
+
+const TargetRegisterClass *
+NDS32RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
+                                                                        const {
+  return &NDS32::GPRRegClass;
+}
+
+void
+NDS32RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
+                                       int SPAdj, unsigned FIOperandNum,
+                                       RegScavenger *RS) const {
+  assert(SPAdj == 0 && "Unexpected");
+  return;
+}
+
+unsigned NDS32RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
+  const NDS32FrameLowering *TFI = getFrameLowering(MF);
+  return TFI->hasFP(MF) ? NDS32::FP : NDS32::SP;
+}

lib/Target/NDS32/NDS32RegisterInfo.td

+//===-- NDS32RegisterInfo.td - NDS32 Register defs -------*- tablegen -*---===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//  Declarations that describe the NDS32 register file
+//===----------------------------------------------------------------------===//
+
+class NDS32Reg<bits<16> Enc, string n> : Register<n> {
+  let HWEncoding = Enc;
+  let Namespace = "NDS32";
+}
+
+class Unallocatable {
+  bit isAllocatable = 0;
+}
+
+
+//===----------------------------------------------------------------------===//
+//  Registers
+//===----------------------------------------------------------------------===//
+
+def R0  : NDS32Reg<0,  "r0">,  DwarfRegNum<[0]>;
+def R1  : NDS32Reg<1,  "r1">,  DwarfRegNum<[1]>;
+def R2  : NDS32Reg<2,  "r2">,  DwarfRegNum<[2]>;
+def R3  : NDS32Reg<3,  "r3">,  DwarfRegNum<[3]>;
+def R4  : NDS32Reg<4,  "r4">,  DwarfRegNum<[4]>;
+def R5  : NDS32Reg<5,  "r5">,  DwarfRegNum<[5]>;
+def R6  : NDS32Reg<6,  "r6">,  DwarfRegNum<[6]>;
+def R7  : NDS32Reg<7,  "r7">,  DwarfRegNum<[7]>;
+def R8  : NDS32Reg<8,  "r8">,  DwarfRegNum<[8]>;
+def R9  : NDS32Reg<9,  "r9">,  DwarfRegNum<[9]>;
+def R10 : NDS32Reg<10, "r10">, DwarfRegNum<[10]>;
+def R11 : NDS32Reg<11, "r11">, DwarfRegNum<[11]>;
+def R12 : NDS32Reg<12, "r12">, DwarfRegNum<[12]>;
+def R13 : NDS32Reg<13, "r13">, DwarfRegNum<[13]>;
+def R14 : NDS32Reg<14, "r14">, DwarfRegNum<[14]>;
+def R15 : NDS32Reg<15, "r15">, DwarfRegNum<[15]>;
+def R16 : NDS32Reg<16, "r16">, DwarfRegNum<[16]>;
+def R17 : NDS32Reg<17, "r17">, DwarfRegNum<[17]>;
+def R18 : NDS32Reg<18, "r18">, DwarfRegNum<[18]>;
+def R19 : NDS32Reg<19, "r19">, DwarfRegNum<[19]>;
+def R20 : NDS32Reg<20, "r20">, DwarfRegNum<[20]>;
+def R21 : NDS32Reg<21, "r21">, DwarfRegNum<[21]>;
+def R22 : NDS32Reg<22, "r22">, DwarfRegNum<[22]>;
+def R23 : NDS32Reg<23, "r23">, DwarfRegNum<[23]>;
+def R24 : NDS32Reg<24, "r24">, DwarfRegNum<[24]>;
+def R25 : NDS32Reg<25, "r25">, DwarfRegNum<[25]>;
+def R26 : NDS32Reg<26, "r26">, DwarfRegNum<[26]>;
+def R27 : NDS32Reg<27, "r27">, DwarfRegNum<[27]>;
+def FP  : NDS32Reg<28, "fp">,  DwarfRegNum<[28]>;
+def GP  : NDS32Reg<29, "gp">,  DwarfRegNum<[29]>;
+def LP  : NDS32Reg<30, "lp">,  DwarfRegNum<[30]>;
+def SP  : NDS32Reg<31, "sp">,  DwarfRegNum<[31]>;
+
+
+def GPR : RegisterClass<"NDS32", [i32], 32,
+  (add  (sequence "R%u", 0, 27),
+   FP, GP, LP, SP)>;
+
+// The low registers for 16 bit instruction, R0-R7.
+def lGPR : RegisterClass<"NDS32", [i32], 32,
+  (add  (sequence "R%u", 0, 7))>;
+
+def FPReg : RegisterClass<"NDS32", [i32], 32, (add FP)>, Unallocatable;
+def SPReg : RegisterClass<"NDS32", [i32], 32, (add SP)>, Unallocatable;
+
+//-----------------------
+// Register Operands.
+
+class NDS32AsmRegOperand : AsmOperandClass {
+  let ParserMethod = "parseAnyRegister";
+}
+
+def GPRAsmOperand : NDS32AsmRegOperand {
+  let Name = "GPRAsmReg";
+  let PredicateMethod = "isGPRAsmReg";
+}
+
+def GPROpnd : RegisterOperand<GPR> {
+  let ParserMatchClass = GPRAsmOperand;
+}