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[X86][AVX512BW] Vectorize v64i8 vector shifts
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Authored by RKSimon on Jan 7 2017, 10:58 AM.

Details

Summary

Shift costs will be added shortly - I'm still simplifying the cost tables to correctly support this.

Diff Detail

Repository
rL LLVM

Event Timeline

RKSimon updated this revision to Diff 83529.Jan 7 2017, 10:58 AM
RKSimon retitled this revision from to [X86][AVX512BW] Vectorize v64i8 vector shifts.
RKSimon updated this object.
RKSimon added reviewers: delena, igorb, craig.topper.
RKSimon set the repository for this revision to rL LLVM.
RKSimon added a subscriber: llvm-commits.
craig.topper added inline comments.Jan 7 2017, 8:53 PM
lib/Target/X86/X86ISelLowering.cpp
21544 ↗(On Diff #83529)

Isn't hasBWI() already implied by the earlier if? Can a 512BitVector get here without BWI?

RKSimon added inline comments.Jan 8 2017, 2:13 AM
lib/Target/X86/X86ISelLowering.cpp
21544 ↗(On Diff #83529)

This is a legacy from some tests to try and get AVX512BWVL targets to use this as well for 128/256 cases - I'll clear it up. Incidently is it worth trying to use the vpmovw2m style instructions to extract the signbits into a mask instead of doing the comparison against zero?

RKSimon updated this revision to Diff 83557.Jan 8 2017, 5:57 AM

Updated sign masked blend to use vpmovb2m instead of vpcmpgtb

RKSimon updated this revision to Diff 83558.Jan 8 2017, 6:38 AM

Added more accurate shift costs

craig.topper accepted this revision.Jan 10 2017, 7:05 PM
craig.topper edited edge metadata.

LGTM

This revision is now accepted and ready to land.Jan 10 2017, 7:05 PM
This revision was automatically updated to reflect the committed changes.