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Differential D28353

[X86] Optimize vector shifts with variable but uniform shift amounts
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Authored by zvi on Jan 5 2017, 5:34 AM.

Details

Reviewers
RKSimon
delena
craig.topper
Commits
rG4b7d724d625d: [X86] Optimize vector shifts with variable but uniform shift amounts
rL291120: [X86] Optimize vector shifts with variable but uniform shift amounts
Summary

For instructions such as PSLLW/PSLLD/PSLLQ a variable shift amount may be passed in an XMM register.
The lower 64-bits of the register are evaluated to determine the shift amount.
This patch improves the construction of the vector containing the shift amount.

Diff Detail

Repository
rL LLVM

Event Timeline

zvi updated this revision to Diff 83224.Jan 5 2017, 5:34 AM
zvi retitled this revision from to [X86] Optimize vector shifts with variable but uniform shift amounts.
zvi updated this object.
zvi added reviewers: craig.topper, delena, RKSimon.
zvi set the repository for this revision to rL LLVM.
zvi added a subscriber: llvm-commits.
RKSimon accepted this revision.Jan 5 2017, 7:15 AM
RKSimon edited edge metadata.

LGTM

This revision is now accepted and ready to land.Jan 5 2017, 7:15 AM
Closed by commit rL291120: [X86] Optimize vector shifts with variable but uniform shift amounts (authored by zvi). · Explain WhyJan 5 2017, 7:22 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

Diff 83234

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

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Show First 20 Lines • Show All 18,300 Lines • ▼ Show 20 Linesstatic SDValue getTargetVShiftNode(unsigned Opc, const SDLoc &dl, MVT VT,
// Change opcode to non-immediate version // Change opcode to non-immediate version
switch (Opc) { switch (Opc) {
default: llvm_unreachable("Unknown target vector shift node"); default: llvm_unreachable("Unknown target vector shift node");
case X86ISD::VSHLI: Opc = X86ISD::VSHL; break; case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
case X86ISD::VSRLI: Opc = X86ISD::VSRL; break; case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
case X86ISD::VSRAI: Opc = X86ISD::VSRA; break; case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
} }
// Need to build a vector containing shift amount.
// SSE/AVX packed shifts only use the lower 64-bit of the shift count.
// +=================+============+=======================================+
// | ShAmt is | HasSSE4.1? | Construct ShAmt vector as |
// +=================+============+=======================================+
// | i64 | Yes, No | Use ShAmt as lowest elt |
// | i32 | Yes | zero-extend in-reg |
// | (i32 zext(i16)) | Yes | zero-extend in-reg |
// | i16/i32 | No | v4i32 build_vector(ShAmt, 0, ud, ud)) |
// +=================+============+=======================================+
const X86Subtarget &Subtarget = const X86Subtarget &Subtarget =
static_cast<const X86Subtarget &>(DAG.getSubtarget()); static_cast<const X86Subtarget &>(DAG.getSubtarget());
if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND && if (SVT == MVT::i64)
ShAmt = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(ShAmt), MVT::v2i64, ShAmt);
else if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) { ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
// Let the shuffle legalizer expand this shift amount node.
SDValue Op0 = ShAmt.getOperand(0); SDValue Op0 = ShAmt.getOperand(0);
Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0); Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, Subtarget, DAG); ShAmt = DAG.getZeroExtendVectorInReg(Op0, SDLoc(Op0), MVT::v2i64);
} else { } else if (Subtarget.hasSSE41() &&
// Need to build a vector containing shift amount. ShAmt.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
// SSE/AVX packed shifts only use the lower 64-bit of the shift count. ShAmt = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(ShAmt), MVT::v4i32, ShAmt);
SmallVector<SDValue, 4> ShOps; ShAmt = DAG.getZeroExtendVectorInReg(ShAmt, SDLoc(ShAmt), MVT::v2i64);
ShOps.push_back(ShAmt); } else {
if (SVT == MVT::i32) { SmallVector<SDValue, 4> ShOps = {ShAmt, DAG.getConstant(0, dl, SVT),
ShOps.push_back(DAG.getConstant(0, dl, SVT)); DAG.getUNDEF(SVT), DAG.getUNDEF(SVT)};
ShOps.push_back(DAG.getUNDEF(SVT)); ShAmt = DAG.getBuildVector(MVT::v4i32, dl, ShOps);
}
ShOps.push_back(DAG.getUNDEF(SVT));
MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
ShAmt = DAG.getBuildVector(BVT, dl, ShOps);
} }
// The return type has to be a 128-bit type with the same element // The return type has to be a 128-bit type with the same element
// type as the input type. // type as the input type.
MVT EltVT = VT.getVectorElementType(); MVT EltVT = VT.getVectorElementType();
MVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits()); MVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
ShAmt = DAG.getBitcast(ShVT, ShAmt); ShAmt = DAG.getBitcast(ShVT, ShAmt);
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llvm/trunk/test/CodeGen/X86/lower-vec-shift-2.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s --check-prefix=SSE2 ; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s --check-prefix=SSE2
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s --check-prefix=AVX ; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s --check-prefix=AVX
define <8 x i16> @test1(<8 x i16> %A, <8 x i16> %B) { define <8 x i16> @test1(<8 x i16> %A, <8 x i16> %B) {
; SSE2-LABEL: test1: ; SSE2-LABEL: test1:
; SSE2: # BB#0: # %entry ; SSE2: # BB#0: # %entry
; SSE2-NEXT: pextrw $0, %xmm1, %eax ; SSE2-NEXT: pextrw $0, %xmm1, %eax
; SSE2-NEXT: movd %eax, %xmm1 ; SSE2-NEXT: movd %eax, %xmm1
; SSE2-NEXT: psllw %xmm1, %xmm0 ; SSE2-NEXT: psllw %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; AVX-LABEL: test1: ; AVX-LABEL: test1:
; AVX: # BB#0: # %entry ; AVX: # BB#0: # %entry
; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
; AVX-NEXT: vpsllw %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpsllw %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
entry: entry:
%vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer %vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer
%shl = shl <8 x i16> %A, %vecinit14 %shl = shl <8 x i16> %A, %vecinit14
ret <8 x i16> %shl ret <8 x i16> %shl
} }
define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) { define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) {
; SSE2-LABEL: test2: ; SSE2-LABEL: test2:
; SSE2: # BB#0: # %entry ; SSE2: # BB#0: # %entry
; SSE2-NEXT: xorps %xmm2, %xmm2 ; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; SSE2-NEXT: pslld %xmm2, %xmm0 ; SSE2-NEXT: pslld %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; AVX-LABEL: test2: ; AVX-LABEL: test2:
; AVX: # BB#0: # %entry ; AVX: # BB#0: # %entry
; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; AVX-NEXT: vpslld %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpslld %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
entry: entry:
%vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer %vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
%shl = shl <4 x i32> %A, %vecinit6 %shl = shl <4 x i32> %A, %vecinit6
ret <4 x i32> %shl ret <4 x i32> %shl
} }
Show All 18 Lines
; SSE2: # BB#0: # %entry ; SSE2: # BB#0: # %entry
; SSE2-NEXT: pextrw $0, %xmm1, %eax ; SSE2-NEXT: pextrw $0, %xmm1, %eax
; SSE2-NEXT: movd %eax, %xmm1 ; SSE2-NEXT: movd %eax, %xmm1
; SSE2-NEXT: psrlw %xmm1, %xmm0 ; SSE2-NEXT: psrlw %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; AVX-LABEL: test4: ; AVX-LABEL: test4:
; AVX: # BB#0: # %entry ; AVX: # BB#0: # %entry
; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
; AVX-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
entry: entry:
%vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer %vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer
%shr = lshr <8 x i16> %A, %vecinit14 %shr = lshr <8 x i16> %A, %vecinit14
ret <8 x i16> %shr ret <8 x i16> %shr
} }
define <4 x i32> @test5(<4 x i32> %A, <4 x i32> %B) { define <4 x i32> @test5(<4 x i32> %A, <4 x i32> %B) {
; SSE2-LABEL: test5: ; SSE2-LABEL: test5:
; SSE2: # BB#0: # %entry ; SSE2: # BB#0: # %entry
; SSE2-NEXT: xorps %xmm2, %xmm2 ; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; SSE2-NEXT: psrld %xmm2, %xmm0 ; SSE2-NEXT: psrld %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; AVX-LABEL: test5: ; AVX-LABEL: test5:
; AVX: # BB#0: # %entry ; AVX: # BB#0: # %entry
; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; AVX-NEXT: vpsrld %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpsrld %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
entry: entry:
%vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer %vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
%shr = lshr <4 x i32> %A, %vecinit6 %shr = lshr <4 x i32> %A, %vecinit6
ret <4 x i32> %shr ret <4 x i32> %shr
} }
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; SSE2: # BB#0: # %entry ; SSE2: # BB#0: # %entry
; SSE2-NEXT: pextrw $0, %xmm1, %eax ; SSE2-NEXT: pextrw $0, %xmm1, %eax
; SSE2-NEXT: movd %eax, %xmm1 ; SSE2-NEXT: movd %eax, %xmm1
; SSE2-NEXT: psraw %xmm1, %xmm0 ; SSE2-NEXT: psraw %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; AVX-LABEL: test7: ; AVX-LABEL: test7:
; AVX: # BB#0: # %entry ; AVX: # BB#0: # %entry
; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
; AVX-NEXT: vpsraw %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpsraw %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
entry: entry:
%vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer %vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer
%shr = ashr <8 x i16> %A, %vecinit14 %shr = ashr <8 x i16> %A, %vecinit14
ret <8 x i16> %shr ret <8 x i16> %shr
} }
define <4 x i32> @test8(<4 x i32> %A, <4 x i32> %B) { define <4 x i32> @test8(<4 x i32> %A, <4 x i32> %B) {
; SSE2-LABEL: test8: ; SSE2-LABEL: test8:
; SSE2: # BB#0: # %entry ; SSE2: # BB#0: # %entry
; SSE2-NEXT: xorps %xmm2, %xmm2 ; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; SSE2-NEXT: psrad %xmm2, %xmm0 ; SSE2-NEXT: psrad %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; AVX-LABEL: test8: ; AVX-LABEL: test8:
; AVX: # BB#0: # %entry ; AVX: # BB#0: # %entry
; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; AVX-NEXT: vpsrad %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpsrad %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
entry: entry:
%vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer %vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
%shr = ashr <4 x i32> %A, %vecinit6 %shr = ashr <4 x i32> %A, %vecinit6
ret <4 x i32> %shr ret <4 x i32> %shr
} }

llvm/trunk/test/CodeGen/X86/vector-rotate-128.ll

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
; ;
; X32-SSE-LABEL: var_rotate_v2i64: ; X32-SSE-LABEL: var_rotate_v2i64:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [64,0,64,0] ; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [64,0,64,0]
; X32-SSE-NEXT: psubq %xmm1, %xmm2 ; X32-SSE-NEXT: psubq %xmm1, %xmm2
; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1] ; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
; X32-SSE-NEXT: movdqa %xmm0, %xmm4 ; X32-SSE-NEXT: movdqa %xmm0, %xmm4
; X32-SSE-NEXT: psllq %xmm3, %xmm4 ; X32-SSE-NEXT: psllq %xmm3, %xmm4
; X32-SSE-NEXT: movq {{.*#+}} xmm1 = xmm1[0],zero
; X32-SSE-NEXT: movdqa %xmm0, %xmm3 ; X32-SSE-NEXT: movdqa %xmm0, %xmm3
; X32-SSE-NEXT: psllq %xmm1, %xmm3 ; X32-SSE-NEXT: psllq %xmm1, %xmm3
; X32-SSE-NEXT: movsd {{.*#+}} xmm4 = xmm3[0],xmm4[1] ; X32-SSE-NEXT: movsd {{.*#+}} xmm4 = xmm3[0],xmm4[1]
; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[2,3,0,1] ; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[2,3,0,1]
; X32-SSE-NEXT: movdqa %xmm0, %xmm1 ; X32-SSE-NEXT: movdqa %xmm0, %xmm1
; X32-SSE-NEXT: psrlq %xmm3, %xmm1 ; X32-SSE-NEXT: psrlq %xmm3, %xmm1
; X32-SSE-NEXT: movq {{.*#+}} xmm2 = xmm2[0],zero
; X32-SSE-NEXT: psrlq %xmm2, %xmm0 ; X32-SSE-NEXT: psrlq %xmm2, %xmm0
; X32-SSE-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] ; X32-SSE-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
; X32-SSE-NEXT: orpd %xmm4, %xmm1 ; X32-SSE-NEXT: orpd %xmm4, %xmm1
; X32-SSE-NEXT: movapd %xmm1, %xmm0 ; X32-SSE-NEXT: movapd %xmm1, %xmm0
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
%b64 = sub <2 x i64> <i64 64, i64 64>, %b %b64 = sub <2 x i64> <i64 64, i64 64>, %b
%shl = shl <2 x i64> %a, %b %shl = shl <2 x i64> %a, %b
%lshr = lshr <2 x i64> %a, %b64 %lshr = lshr <2 x i64> %a, %b64
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llvm/trunk/test/CodeGen/X86/vector-shift-ashr-128.ll

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
; AVX512-NEXT: vpsrlvq %xmm1, %xmm2, %xmm3 ; AVX512-NEXT: vpsrlvq %xmm1, %xmm2, %xmm3
; AVX512-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; AVX512-NEXT: vpxor %xmm2, %xmm0, %xmm0
; AVX512-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpsubq %xmm3, %xmm0, %xmm0 ; AVX512-NEXT: vpsubq %xmm3, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
; ;
; X32-SSE-LABEL: var_shift_v2i64: ; X32-SSE-LABEL: var_shift_v2i64:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1] ; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
; X32-SSE-NEXT: movdqa {{.*#+}} xmm3 = [0,2147483648,0,2147483648] ; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [0,2147483648,0,2147483648]
; X32-SSE-NEXT: movdqa %xmm3, %xmm4 ; X32-SSE-NEXT: movdqa %xmm2, %xmm4
; X32-SSE-NEXT: psrlq %xmm2, %xmm4 ; X32-SSE-NEXT: psrlq %xmm3, %xmm4
; X32-SSE-NEXT: movq {{.*#+}} xmm5 = xmm1[0],zero ; X32-SSE-NEXT: psrlq %xmm1, %xmm2
; X32-SSE-NEXT: psrlq %xmm5, %xmm3 ; X32-SSE-NEXT: movsd {{.*#+}} xmm4 = xmm2[0],xmm4[1]
; X32-SSE-NEXT: movsd {{.*#+}} xmm4 = xmm3[0],xmm4[1] ; X32-SSE-NEXT: movdqa %xmm0, %xmm2
; X32-SSE-NEXT: movdqa %xmm0, %xmm1 ; X32-SSE-NEXT: psrlq %xmm3, %xmm2
; X32-SSE-NEXT: psrlq %xmm2, %xmm1 ; X32-SSE-NEXT: psrlq %xmm1, %xmm0
; X32-SSE-NEXT: psrlq %xmm5, %xmm0 ; X32-SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
; X32-SSE-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] ; X32-SSE-NEXT: xorpd %xmm4, %xmm2
; X32-SSE-NEXT: xorpd %xmm4, %xmm1 ; X32-SSE-NEXT: psubq %xmm4, %xmm2
; X32-SSE-NEXT: psubq %xmm4, %xmm1 ; X32-SSE-NEXT: movdqa %xmm2, %xmm0
; X32-SSE-NEXT: movdqa %xmm1, %xmm0
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
%shift = ashr <2 x i64> %a, %b %shift = ashr <2 x i64> %a, %b
ret <2 x i64> %shift ret <2 x i64> %shift
} }
define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind { define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
; SSE2-LABEL: var_shift_v4i32: ; SSE2-LABEL: var_shift_v4i32:
; SSE2: # BB#0: ; SSE2: # BB#0:
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; AVX512-NEXT: vpsrlq %xmm1, %xmm2, %xmm2 ; AVX512-NEXT: vpsrlq %xmm1, %xmm2, %xmm2
; AVX512-NEXT: vpsrlq %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpsrlq %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; AVX512-NEXT: vpxor %xmm2, %xmm0, %xmm0
; AVX512-NEXT: vpsubq %xmm2, %xmm0, %xmm0 ; AVX512-NEXT: vpsubq %xmm2, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
; ;
; X32-SSE-LABEL: splatvar_shift_v2i64: ; X32-SSE-LABEL: splatvar_shift_v2i64:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: movq {{.*#+}} xmm1 = xmm1[0],zero
; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [0,2147483648,0,2147483648] ; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [0,2147483648,0,2147483648]
; X32-SSE-NEXT: psrlq %xmm1, %xmm2 ; X32-SSE-NEXT: psrlq %xmm1, %xmm2
; X32-SSE-NEXT: psrlq %xmm1, %xmm0 ; X32-SSE-NEXT: psrlq %xmm1, %xmm0
; X32-SSE-NEXT: pxor %xmm2, %xmm0 ; X32-SSE-NEXT: pxor %xmm2, %xmm0
; X32-SSE-NEXT: psubq %xmm2, %xmm0 ; X32-SSE-NEXT: psubq %xmm2, %xmm0
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
%splat = shufflevector <2 x i64> %b, <2 x i64> undef, <2 x i32> zeroinitializer %splat = shufflevector <2 x i64> %b, <2 x i64> undef, <2 x i32> zeroinitializer
%shift = ashr <2 x i64> %a, %splat %shift = ashr <2 x i64> %a, %splat
ret <2 x i64> %shift ret <2 x i64> %shift
} }
define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind { define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
; SSE2-LABEL: splatvar_shift_v4i32: ; SSE2-LABEL: splatvar_shift_v4i32:
; SSE2: # BB#0: ; SSE2: # BB#0:
; SSE2-NEXT: xorps %xmm2, %xmm2 ; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; SSE2-NEXT: psrad %xmm2, %xmm0 ; SSE2-NEXT: psrad %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: splatvar_shift_v4i32: ; SSE41-LABEL: splatvar_shift_v4i32:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: pxor %xmm2, %xmm2 ; SSE41-NEXT: pmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3,4,5,6,7] ; SSE41-NEXT: psrad %xmm1, %xmm0
; SSE41-NEXT: psrad %xmm2, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: splatvar_shift_v4i32: ; AVX-LABEL: splatvar_shift_v4i32:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; AVX-NEXT: vpsrad %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpsrad %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; XOP-LABEL: splatvar_shift_v4i32: ; XOP-LABEL: splatvar_shift_v4i32:
; XOP: # BB#0: ; XOP: # BB#0:
; XOP-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; XOP-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; XOP-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; XOP-NEXT: vpsrad %xmm1, %xmm0, %xmm0 ; XOP-NEXT: vpsrad %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; AVX512-LABEL: splatvar_shift_v4i32: ; AVX512-LABEL: splatvar_shift_v4i32:
; AVX512: ## BB#0: ; AVX512: ## BB#0:
; AVX512-NEXT: vxorps %xmm2, %xmm2, %xmm2 ; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX512-NEXT: vmovss {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3]
; AVX512-NEXT: vpsrad %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpsrad %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
; ;
; X32-SSE-LABEL: splatvar_shift_v4i32: ; X32-SSE-LABEL: splatvar_shift_v4i32:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: xorps %xmm2, %xmm2 ; X32-SSE-NEXT: xorps %xmm2, %xmm2
; X32-SSE-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] ; X32-SSE-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; X32-SSE-NEXT: psrad %xmm2, %xmm0 ; X32-SSE-NEXT: psrad %xmm2, %xmm0
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
%splat = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer %splat = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer
%shift = ashr <4 x i32> %a, %splat %shift = ashr <4 x i32> %a, %splat
ret <4 x i32> %shift ret <4 x i32> %shift
} }
define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind { define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
; SSE2-LABEL: splatvar_shift_v8i16: ; SSE2-LABEL: splatvar_shift_v8i16:
; SSE2: # BB#0: ; SSE2: # BB#0:
; SSE2-NEXT: pextrw $0, %xmm1, %eax ; SSE2-NEXT: pextrw $0, %xmm1, %eax
; SSE2-NEXT: movd %eax, %xmm1 ; SSE2-NEXT: movd %eax, %xmm1
; SSE2-NEXT: psraw %xmm1, %xmm0 ; SSE2-NEXT: psraw %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: splatvar_shift_v8i16: ; SSE41-LABEL: splatvar_shift_v8i16:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: pxor %xmm2, %xmm2 ; SSE41-NEXT: pmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3,4,5,6,7] ; SSE41-NEXT: psraw %xmm1, %xmm0
; SSE41-NEXT: psraw %xmm2, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: splatvar_shift_v8i16: ; AVX-LABEL: splatvar_shift_v8i16:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
; AVX-NEXT: vpsraw %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpsraw %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; XOP-LABEL: splatvar_shift_v8i16: ; XOP-LABEL: splatvar_shift_v8i16:
; XOP: # BB#0: ; XOP: # BB#0:
; XOP-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; XOP-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; XOP-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
; XOP-NEXT: vpsraw %xmm1, %xmm0, %xmm0 ; XOP-NEXT: vpsraw %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; AVX512-LABEL: splatvar_shift_v8i16: ; AVX512-LABEL: splatvar_shift_v8i16:
; AVX512: ## BB#0: ; AVX512: ## BB#0:
; AVX512-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX512-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
; AVX512-NEXT: vpsraw %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpsraw %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
; ;
; X32-SSE-LABEL: splatvar_shift_v8i16: ; X32-SSE-LABEL: splatvar_shift_v8i16:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pextrw $0, %xmm1, %eax ; X32-SSE-NEXT: pextrw $0, %xmm1, %eax
; X32-SSE-NEXT: movd %eax, %xmm1 ; X32-SSE-NEXT: movd %eax, %xmm1
; X32-SSE-NEXT: psraw %xmm1, %xmm0 ; X32-SSE-NEXT: psraw %xmm1, %xmm0
▲ Show 20 Lines • Show All 914 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-shift-ashr-256.ll

Show First 20 Lines • Show All 420 Lines • ▼ Show 20 Lines; AVX512-NEXT: retq
%splat = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> zeroinitializer %splat = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> zeroinitializer
%shift = ashr <4 x i64> %a, %splat %shift = ashr <4 x i64> %a, %splat
ret <4 x i64> %shift ret <4 x i64> %shift
} }
define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind { define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
; AVX1-LABEL: splatvar_shift_v8i32: ; AVX1-LABEL: splatvar_shift_v8i32:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX1-NEXT: vpsrad %xmm1, %xmm2, %xmm2 ; AVX1-NEXT: vpsrad %xmm1, %xmm2, %xmm2
; AVX1-NEXT: vpsrad %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpsrad %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: splatvar_shift_v8i32: ; AVX2-LABEL: splatvar_shift_v8i32:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX2-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; AVX2-NEXT: vpsrad %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: vpsrad %xmm1, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; XOPAVX1-LABEL: splatvar_shift_v8i32: ; XOPAVX1-LABEL: splatvar_shift_v8i32:
; XOPAVX1: # BB#0: ; XOPAVX1: # BB#0:
; XOPAVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; XOPAVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; XOPAVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; XOPAVX1-NEXT: vpsrad %xmm1, %xmm2, %xmm2 ; XOPAVX1-NEXT: vpsrad %xmm1, %xmm2, %xmm2
; XOPAVX1-NEXT: vpsrad %xmm1, %xmm0, %xmm0 ; XOPAVX1-NEXT: vpsrad %xmm1, %xmm0, %xmm0
; XOPAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; XOPAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; XOPAVX1-NEXT: retq ; XOPAVX1-NEXT: retq
; ;
; XOPAVX2-LABEL: splatvar_shift_v8i32: ; XOPAVX2-LABEL: splatvar_shift_v8i32:
; XOPAVX2: # BB#0: ; XOPAVX2: # BB#0:
; XOPAVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; XOPAVX2-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; XOPAVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; XOPAVX2-NEXT: vpsrad %xmm1, %ymm0, %ymm0 ; XOPAVX2-NEXT: vpsrad %xmm1, %ymm0, %ymm0
; XOPAVX2-NEXT: retq ; XOPAVX2-NEXT: retq
; ;
; AVX512-LABEL: splatvar_shift_v8i32: ; AVX512-LABEL: splatvar_shift_v8i32:
; AVX512: ## BB#0: ; AVX512: ## BB#0:
; AVX512-NEXT: vxorps %xmm2, %xmm2, %xmm2 ; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX512-NEXT: vmovss {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3]
; AVX512-NEXT: vpsrad %xmm1, %ymm0, %ymm0 ; AVX512-NEXT: vpsrad %xmm1, %ymm0, %ymm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%splat = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> zeroinitializer %splat = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> zeroinitializer
%shift = ashr <8 x i32> %a, %splat %shift = ashr <8 x i32> %a, %splat
ret <8 x i32> %shift ret <8 x i32> %shift
} }
define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind { define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind {
; AVX1-LABEL: splatvar_shift_v16i16: ; AVX1-LABEL: splatvar_shift_v16i16:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpextrw $0, %xmm1, %eax ; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX1-NEXT: vmovd %eax, %xmm1
; AVX1-NEXT: vpsraw %xmm1, %xmm2, %xmm2 ; AVX1-NEXT: vpsraw %xmm1, %xmm2, %xmm2
; AVX1-NEXT: vpsraw %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpsraw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: splatvar_shift_v16i16: ; AVX2-LABEL: splatvar_shift_v16i16:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpextrw $0, %xmm1, %eax ; AVX2-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX2-NEXT: vmovd %eax, %xmm1
; AVX2-NEXT: vpsraw %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: vpsraw %xmm1, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; XOPAVX1-LABEL: splatvar_shift_v16i16: ; XOPAVX1-LABEL: splatvar_shift_v16i16:
; XOPAVX1: # BB#0: ; XOPAVX1: # BB#0:
; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; XOPAVX1-NEXT: vpextrw $0, %xmm1, %eax ; XOPAVX1-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; XOPAVX1-NEXT: vmovd %eax, %xmm1
; XOPAVX1-NEXT: vpsraw %xmm1, %xmm2, %xmm2 ; XOPAVX1-NEXT: vpsraw %xmm1, %xmm2, %xmm2
; XOPAVX1-NEXT: vpsraw %xmm1, %xmm0, %xmm0 ; XOPAVX1-NEXT: vpsraw %xmm1, %xmm0, %xmm0
; XOPAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; XOPAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; XOPAVX1-NEXT: retq ; XOPAVX1-NEXT: retq
; ;
; XOPAVX2-LABEL: splatvar_shift_v16i16: ; XOPAVX2-LABEL: splatvar_shift_v16i16:
; XOPAVX2: # BB#0: ; XOPAVX2: # BB#0:
; XOPAVX2-NEXT: vpextrw $0, %xmm1, %eax ; XOPAVX2-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; XOPAVX2-NEXT: vmovd %eax, %xmm1
; XOPAVX2-NEXT: vpsraw %xmm1, %ymm0, %ymm0 ; XOPAVX2-NEXT: vpsraw %xmm1, %ymm0, %ymm0
; XOPAVX2-NEXT: retq ; XOPAVX2-NEXT: retq
; ;
; AVX512-LABEL: splatvar_shift_v16i16: ; AVX512-LABEL: splatvar_shift_v16i16:
; AVX512: ## BB#0: ; AVX512: ## BB#0:
; AVX512-NEXT: vpextrw $0, %xmm1, %eax ; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX512-NEXT: vmovd %eax, %xmm1
; AVX512-NEXT: vpsraw %xmm1, %ymm0, %ymm0 ; AVX512-NEXT: vpsraw %xmm1, %ymm0, %ymm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%splat = shufflevector <16 x i16> %b, <16 x i16> undef, <16 x i32> zeroinitializer %splat = shufflevector <16 x i16> %b, <16 x i16> undef, <16 x i32> zeroinitializer
%shift = ashr <16 x i16> %a, %splat %shift = ashr <16 x i16> %a, %splat
ret <16 x i16> %shift ret <16 x i16> %shift
} }
define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
▲ Show 20 Lines • Show All 617 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-shift-ashr-512.ll

Show First 20 Lines • Show All 519 Lines • ▼ Show 20 Lines; ALL-NEXT: retq
%splat = shufflevector <8 x i64> %b, <8 x i64> undef, <8 x i32> zeroinitializer %splat = shufflevector <8 x i64> %b, <8 x i64> undef, <8 x i32> zeroinitializer
%shift = ashr <8 x i64> %a, %splat %shift = ashr <8 x i64> %a, %splat
ret <8 x i64> %shift ret <8 x i64> %shift
} }
define <16 x i32> @splatvar_shift_v16i32(<16 x i32> %a, <16 x i32> %b) nounwind { define <16 x i32> @splatvar_shift_v16i32(<16 x i32> %a, <16 x i32> %b) nounwind {
; ALL-LABEL: splatvar_shift_v16i32: ; ALL-LABEL: splatvar_shift_v16i32:
; ALL: ## BB#0: ; ALL: ## BB#0:
; ALL-NEXT: vxorps %xmm2, %xmm2, %xmm2 ; ALL-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; ALL-NEXT: vmovss {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3]
; ALL-NEXT: vpsrad %xmm1, %zmm0, %zmm0 ; ALL-NEXT: vpsrad %xmm1, %zmm0, %zmm0
; ALL-NEXT: retq ; ALL-NEXT: retq
%splat = shufflevector <16 x i32> %b, <16 x i32> undef, <16 x i32> zeroinitializer %splat = shufflevector <16 x i32> %b, <16 x i32> undef, <16 x i32> zeroinitializer
%shift = ashr <16 x i32> %a, %splat %shift = ashr <16 x i32> %a, %splat
ret <16 x i32> %shift ret <16 x i32> %shift
} }
define <32 x i16> @splatvar_shift_v32i16(<32 x i16> %a, <32 x i16> %b) nounwind { define <32 x i16> @splatvar_shift_v32i16(<32 x i16> %a, <32 x i16> %b) nounwind {
; AVX512DQ-LABEL: splatvar_shift_v32i16: ; AVX512DQ-LABEL: splatvar_shift_v32i16:
; AVX512DQ: ## BB#0: ; AVX512DQ: ## BB#0:
; AVX512DQ-NEXT: vpextrw $0, %xmm2, %eax ; AVX512DQ-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero
; AVX512DQ-NEXT: vmovd %eax, %xmm2
; AVX512DQ-NEXT: vpsraw %xmm2, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpsraw %xmm2, %ymm0, %ymm0
; AVX512DQ-NEXT: vpsraw %xmm2, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpsraw %xmm2, %ymm1, %ymm1
; AVX512DQ-NEXT: retq ; AVX512DQ-NEXT: retq
; ;
; AVX512BW-LABEL: splatvar_shift_v32i16: ; AVX512BW-LABEL: splatvar_shift_v32i16:
; AVX512BW: ## BB#0: ; AVX512BW: ## BB#0:
; AVX512BW-NEXT: vpextrw $0, %xmm1, %eax ; AVX512BW-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX512BW-NEXT: vmovd %eax, %xmm1
; AVX512BW-NEXT: vpsraw %xmm1, %zmm0, %zmm0 ; AVX512BW-NEXT: vpsraw %xmm1, %zmm0, %zmm0
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
%splat = shufflevector <32 x i16> %b, <32 x i16> undef, <32 x i32> zeroinitializer %splat = shufflevector <32 x i16> %b, <32 x i16> undef, <32 x i32> zeroinitializer
%shift = ashr <32 x i16> %a, %splat %shift = ashr <32 x i16> %a, %splat
ret <32 x i16> %shift ret <32 x i16> %shift
} }
define <64 x i8> @splatvar_shift_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind { define <64 x i8> @splatvar_shift_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
▲ Show 20 Lines • Show All 882 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-shift-lshr-128.ll

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; AVX512-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
; ;
; X32-SSE-LABEL: var_shift_v2i64: ; X32-SSE-LABEL: var_shift_v2i64:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1] ; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
; X32-SSE-NEXT: movdqa %xmm0, %xmm2 ; X32-SSE-NEXT: movdqa %xmm0, %xmm2
; X32-SSE-NEXT: psrlq %xmm3, %xmm2 ; X32-SSE-NEXT: psrlq %xmm3, %xmm2
; X32-SSE-NEXT: movq {{.*#+}} xmm1 = xmm1[0],zero
; X32-SSE-NEXT: psrlq %xmm1, %xmm0 ; X32-SSE-NEXT: psrlq %xmm1, %xmm0
; X32-SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] ; X32-SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
; X32-SSE-NEXT: movapd %xmm2, %xmm0 ; X32-SSE-NEXT: movapd %xmm2, %xmm0
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
%shift = lshr <2 x i64> %a, %b %shift = lshr <2 x i64> %a, %b
ret <2 x i64> %shift ret <2 x i64> %shift
} }
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; ;
; AVX512-LABEL: splatvar_shift_v2i64: ; AVX512-LABEL: splatvar_shift_v2i64:
; AVX512: ## BB#0: ; AVX512: ## BB#0:
; AVX512-NEXT: vpsrlq %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpsrlq %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
; ;
; X32-SSE-LABEL: splatvar_shift_v2i64: ; X32-SSE-LABEL: splatvar_shift_v2i64:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: movq {{.*#+}} xmm1 = xmm1[0],zero
; X32-SSE-NEXT: psrlq %xmm1, %xmm0 ; X32-SSE-NEXT: psrlq %xmm1, %xmm0
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
%splat = shufflevector <2 x i64> %b, <2 x i64> undef, <2 x i32> zeroinitializer %splat = shufflevector <2 x i64> %b, <2 x i64> undef, <2 x i32> zeroinitializer
%shift = lshr <2 x i64> %a, %splat %shift = lshr <2 x i64> %a, %splat
ret <2 x i64> %shift ret <2 x i64> %shift
} }
define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind { define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
; SSE2-LABEL: splatvar_shift_v4i32: ; SSE2-LABEL: splatvar_shift_v4i32:
; SSE2: # BB#0: ; SSE2: # BB#0:
; SSE2-NEXT: xorps %xmm2, %xmm2 ; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; SSE2-NEXT: psrld %xmm2, %xmm0 ; SSE2-NEXT: psrld %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: splatvar_shift_v4i32: ; SSE41-LABEL: splatvar_shift_v4i32:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: pxor %xmm2, %xmm2 ; SSE41-NEXT: pmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3,4,5,6,7] ; SSE41-NEXT: psrld %xmm1, %xmm0
; SSE41-NEXT: psrld %xmm2, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: splatvar_shift_v4i32: ; AVX-LABEL: splatvar_shift_v4i32:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; AVX-NEXT: vpsrld %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpsrld %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; XOP-LABEL: splatvar_shift_v4i32: ; XOP-LABEL: splatvar_shift_v4i32:
; XOP: # BB#0: ; XOP: # BB#0:
; XOP-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; XOP-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; XOP-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; XOP-NEXT: vpsrld %xmm1, %xmm0, %xmm0 ; XOP-NEXT: vpsrld %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; AVX512-LABEL: splatvar_shift_v4i32: ; AVX512-LABEL: splatvar_shift_v4i32:
; AVX512: ## BB#0: ; AVX512: ## BB#0:
; AVX512-NEXT: vxorps %xmm2, %xmm2, %xmm2 ; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX512-NEXT: vmovss {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3]
; AVX512-NEXT: vpsrld %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpsrld %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
; ;
; X32-SSE-LABEL: splatvar_shift_v4i32: ; X32-SSE-LABEL: splatvar_shift_v4i32:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: xorps %xmm2, %xmm2 ; X32-SSE-NEXT: xorps %xmm2, %xmm2
; X32-SSE-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] ; X32-SSE-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; X32-SSE-NEXT: psrld %xmm2, %xmm0 ; X32-SSE-NEXT: psrld %xmm2, %xmm0
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
%splat = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer %splat = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer
%shift = lshr <4 x i32> %a, %splat %shift = lshr <4 x i32> %a, %splat
ret <4 x i32> %shift ret <4 x i32> %shift
} }
define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind { define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
; SSE2-LABEL: splatvar_shift_v8i16: ; SSE2-LABEL: splatvar_shift_v8i16:
; SSE2: # BB#0: ; SSE2: # BB#0:
; SSE2-NEXT: pextrw $0, %xmm1, %eax ; SSE2-NEXT: pextrw $0, %xmm1, %eax
; SSE2-NEXT: movd %eax, %xmm1 ; SSE2-NEXT: movd %eax, %xmm1
; SSE2-NEXT: psrlw %xmm1, %xmm0 ; SSE2-NEXT: psrlw %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: splatvar_shift_v8i16: ; SSE41-LABEL: splatvar_shift_v8i16:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: pxor %xmm2, %xmm2 ; SSE41-NEXT: pmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3,4,5,6,7] ; SSE41-NEXT: psrlw %xmm1, %xmm0
; SSE41-NEXT: psrlw %xmm2, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: splatvar_shift_v8i16: ; AVX-LABEL: splatvar_shift_v8i16:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
; AVX-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; XOP-LABEL: splatvar_shift_v8i16: ; XOP-LABEL: splatvar_shift_v8i16:
; XOP: # BB#0: ; XOP: # BB#0:
; XOP-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; XOP-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; XOP-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
; XOP-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 ; XOP-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; AVX512-LABEL: splatvar_shift_v8i16: ; AVX512-LABEL: splatvar_shift_v8i16:
; AVX512: ## BB#0: ; AVX512: ## BB#0:
; AVX512-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX512-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
; AVX512-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
; ;
; X32-SSE-LABEL: splatvar_shift_v8i16: ; X32-SSE-LABEL: splatvar_shift_v8i16:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pextrw $0, %xmm1, %eax ; X32-SSE-NEXT: pextrw $0, %xmm1, %eax
; X32-SSE-NEXT: movd %eax, %xmm1 ; X32-SSE-NEXT: movd %eax, %xmm1
; X32-SSE-NEXT: psrlw %xmm1, %xmm0 ; X32-SSE-NEXT: psrlw %xmm1, %xmm0
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llvm/trunk/test/CodeGen/X86/vector-shift-lshr-256.ll

Show First 20 Lines • Show All 331 Lines • ▼ Show 20 Lines; AVX512-NEXT: retq
%splat = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> zeroinitializer %splat = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> zeroinitializer
%shift = lshr <4 x i64> %a, %splat %shift = lshr <4 x i64> %a, %splat
ret <4 x i64> %shift ret <4 x i64> %shift
} }
define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind { define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
; AVX1-LABEL: splatvar_shift_v8i32: ; AVX1-LABEL: splatvar_shift_v8i32:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX1-NEXT: vpsrld %xmm1, %xmm2, %xmm2 ; AVX1-NEXT: vpsrld %xmm1, %xmm2, %xmm2
; AVX1-NEXT: vpsrld %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpsrld %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: splatvar_shift_v8i32: ; AVX2-LABEL: splatvar_shift_v8i32:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX2-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; AVX2-NEXT: vpsrld %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: vpsrld %xmm1, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; XOPAVX1-LABEL: splatvar_shift_v8i32: ; XOPAVX1-LABEL: splatvar_shift_v8i32:
; XOPAVX1: # BB#0: ; XOPAVX1: # BB#0:
; XOPAVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; XOPAVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; XOPAVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; XOPAVX1-NEXT: vpsrld %xmm1, %xmm2, %xmm2 ; XOPAVX1-NEXT: vpsrld %xmm1, %xmm2, %xmm2
; XOPAVX1-NEXT: vpsrld %xmm1, %xmm0, %xmm0 ; XOPAVX1-NEXT: vpsrld %xmm1, %xmm0, %xmm0
; XOPAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; XOPAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; XOPAVX1-NEXT: retq ; XOPAVX1-NEXT: retq
; ;
; XOPAVX2-LABEL: splatvar_shift_v8i32: ; XOPAVX2-LABEL: splatvar_shift_v8i32:
; XOPAVX2: # BB#0: ; XOPAVX2: # BB#0:
; XOPAVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; XOPAVX2-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; XOPAVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; XOPAVX2-NEXT: vpsrld %xmm1, %ymm0, %ymm0 ; XOPAVX2-NEXT: vpsrld %xmm1, %ymm0, %ymm0
; XOPAVX2-NEXT: retq ; XOPAVX2-NEXT: retq
; ;
; AVX512-LABEL: splatvar_shift_v8i32: ; AVX512-LABEL: splatvar_shift_v8i32:
; AVX512: ## BB#0: ; AVX512: ## BB#0:
; AVX512-NEXT: vxorps %xmm2, %xmm2, %xmm2 ; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX512-NEXT: vmovss {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3]
; AVX512-NEXT: vpsrld %xmm1, %ymm0, %ymm0 ; AVX512-NEXT: vpsrld %xmm1, %ymm0, %ymm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%splat = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> zeroinitializer %splat = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> zeroinitializer
%shift = lshr <8 x i32> %a, %splat %shift = lshr <8 x i32> %a, %splat
ret <8 x i32> %shift ret <8 x i32> %shift
} }
define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind { define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind {
; AVX1-LABEL: splatvar_shift_v16i16: ; AVX1-LABEL: splatvar_shift_v16i16:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpextrw $0, %xmm1, %eax ; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX1-NEXT: vmovd %eax, %xmm1
; AVX1-NEXT: vpsrlw %xmm1, %xmm2, %xmm2 ; AVX1-NEXT: vpsrlw %xmm1, %xmm2, %xmm2
; AVX1-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: splatvar_shift_v16i16: ; AVX2-LABEL: splatvar_shift_v16i16:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpextrw $0, %xmm1, %eax ; AVX2-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX2-NEXT: vmovd %eax, %xmm1
; AVX2-NEXT: vpsrlw %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: vpsrlw %xmm1, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; XOPAVX1-LABEL: splatvar_shift_v16i16: ; XOPAVX1-LABEL: splatvar_shift_v16i16:
; XOPAVX1: # BB#0: ; XOPAVX1: # BB#0:
; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; XOPAVX1-NEXT: vpextrw $0, %xmm1, %eax ; XOPAVX1-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; XOPAVX1-NEXT: vmovd %eax, %xmm1
; XOPAVX1-NEXT: vpsrlw %xmm1, %xmm2, %xmm2 ; XOPAVX1-NEXT: vpsrlw %xmm1, %xmm2, %xmm2
; XOPAVX1-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 ; XOPAVX1-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
; XOPAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; XOPAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; XOPAVX1-NEXT: retq ; XOPAVX1-NEXT: retq
; ;
; XOPAVX2-LABEL: splatvar_shift_v16i16: ; XOPAVX2-LABEL: splatvar_shift_v16i16:
; XOPAVX2: # BB#0: ; XOPAVX2: # BB#0:
; XOPAVX2-NEXT: vpextrw $0, %xmm1, %eax ; XOPAVX2-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; XOPAVX2-NEXT: vmovd %eax, %xmm1
; XOPAVX2-NEXT: vpsrlw %xmm1, %ymm0, %ymm0 ; XOPAVX2-NEXT: vpsrlw %xmm1, %ymm0, %ymm0
; XOPAVX2-NEXT: retq ; XOPAVX2-NEXT: retq
; ;
; AVX512-LABEL: splatvar_shift_v16i16: ; AVX512-LABEL: splatvar_shift_v16i16:
; AVX512: ## BB#0: ; AVX512: ## BB#0:
; AVX512-NEXT: vpextrw $0, %xmm1, %eax ; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX512-NEXT: vmovd %eax, %xmm1
; AVX512-NEXT: vpsrlw %xmm1, %ymm0, %ymm0 ; AVX512-NEXT: vpsrlw %xmm1, %ymm0, %ymm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%splat = shufflevector <16 x i16> %b, <16 x i16> undef, <16 x i32> zeroinitializer %splat = shufflevector <16 x i16> %b, <16 x i16> undef, <16 x i32> zeroinitializer
%shift = lshr <16 x i16> %a, %splat %shift = lshr <16 x i16> %a, %splat
ret <16 x i16> %shift ret <16 x i16> %shift
} }
define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
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llvm/trunk/test/CodeGen/X86/vector-shift-lshr-512.ll

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%splat = shufflevector <8 x i64> %b, <8 x i64> undef, <8 x i32> zeroinitializer %splat = shufflevector <8 x i64> %b, <8 x i64> undef, <8 x i32> zeroinitializer
%shift = lshr <8 x i64> %a, %splat %shift = lshr <8 x i64> %a, %splat
ret <8 x i64> %shift ret <8 x i64> %shift
} }
define <16 x i32> @splatvar_shift_v16i32(<16 x i32> %a, <16 x i32> %b) nounwind { define <16 x i32> @splatvar_shift_v16i32(<16 x i32> %a, <16 x i32> %b) nounwind {
; ALL-LABEL: splatvar_shift_v16i32: ; ALL-LABEL: splatvar_shift_v16i32:
; ALL: ## BB#0: ; ALL: ## BB#0:
; ALL-NEXT: vxorps %xmm2, %xmm2, %xmm2 ; ALL-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; ALL-NEXT: vmovss {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3]
; ALL-NEXT: vpsrld %xmm1, %zmm0, %zmm0 ; ALL-NEXT: vpsrld %xmm1, %zmm0, %zmm0
; ALL-NEXT: retq ; ALL-NEXT: retq
%splat = shufflevector <16 x i32> %b, <16 x i32> undef, <16 x i32> zeroinitializer %splat = shufflevector <16 x i32> %b, <16 x i32> undef, <16 x i32> zeroinitializer
%shift = lshr <16 x i32> %a, %splat %shift = lshr <16 x i32> %a, %splat
ret <16 x i32> %shift ret <16 x i32> %shift
} }
define <32 x i16> @splatvar_shift_v32i16(<32 x i16> %a, <32 x i16> %b) nounwind { define <32 x i16> @splatvar_shift_v32i16(<32 x i16> %a, <32 x i16> %b) nounwind {
; AVX512DQ-LABEL: splatvar_shift_v32i16: ; AVX512DQ-LABEL: splatvar_shift_v32i16:
; AVX512DQ: ## BB#0: ; AVX512DQ: ## BB#0:
; AVX512DQ-NEXT: vpextrw $0, %xmm2, %eax ; AVX512DQ-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero
; AVX512DQ-NEXT: vmovd %eax, %xmm2
; AVX512DQ-NEXT: vpsrlw %xmm2, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpsrlw %xmm2, %ymm0, %ymm0
; AVX512DQ-NEXT: vpsrlw %xmm2, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpsrlw %xmm2, %ymm1, %ymm1
; AVX512DQ-NEXT: retq ; AVX512DQ-NEXT: retq
; ;
; AVX512BW-LABEL: splatvar_shift_v32i16: ; AVX512BW-LABEL: splatvar_shift_v32i16:
; AVX512BW: ## BB#0: ; AVX512BW: ## BB#0:
; AVX512BW-NEXT: vpextrw $0, %xmm1, %eax ; AVX512BW-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX512BW-NEXT: vmovd %eax, %xmm1
; AVX512BW-NEXT: vpsrlw %xmm1, %zmm0, %zmm0 ; AVX512BW-NEXT: vpsrlw %xmm1, %zmm0, %zmm0
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
%splat = shufflevector <32 x i16> %b, <32 x i16> undef, <32 x i32> zeroinitializer %splat = shufflevector <32 x i16> %b, <32 x i16> undef, <32 x i32> zeroinitializer
%shift = lshr <32 x i16> %a, %splat %shift = lshr <32 x i16> %a, %splat
ret <32 x i16> %shift ret <32 x i16> %shift
} }
define <64 x i8> @splatvar_shift_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind { define <64 x i8> @splatvar_shift_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
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llvm/trunk/test/CodeGen/X86/vector-shift-shl-128.ll

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; AVX512-NEXT: vpsllvq %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
; ;
; X32-SSE-LABEL: var_shift_v2i64: ; X32-SSE-LABEL: var_shift_v2i64:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1] ; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
; X32-SSE-NEXT: movdqa %xmm0, %xmm2 ; X32-SSE-NEXT: movdqa %xmm0, %xmm2
; X32-SSE-NEXT: psllq %xmm3, %xmm2 ; X32-SSE-NEXT: psllq %xmm3, %xmm2
; X32-SSE-NEXT: movq {{.*#+}} xmm1 = xmm1[0],zero
; X32-SSE-NEXT: psllq %xmm1, %xmm0 ; X32-SSE-NEXT: psllq %xmm1, %xmm0
; X32-SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] ; X32-SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
; X32-SSE-NEXT: movapd %xmm2, %xmm0 ; X32-SSE-NEXT: movapd %xmm2, %xmm0
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
%shift = shl <2 x i64> %a, %b %shift = shl <2 x i64> %a, %b
ret <2 x i64> %shift ret <2 x i64> %shift
} }
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; ;
; AVX512-LABEL: splatvar_shift_v2i64: ; AVX512-LABEL: splatvar_shift_v2i64:
; AVX512: ## BB#0: ; AVX512: ## BB#0:
; AVX512-NEXT: vpsllq %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpsllq %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
; ;
; X32-SSE-LABEL: splatvar_shift_v2i64: ; X32-SSE-LABEL: splatvar_shift_v2i64:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: movq {{.*#+}} xmm1 = xmm1[0],zero
; X32-SSE-NEXT: psllq %xmm1, %xmm0 ; X32-SSE-NEXT: psllq %xmm1, %xmm0
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
%splat = shufflevector <2 x i64> %b, <2 x i64> undef, <2 x i32> zeroinitializer %splat = shufflevector <2 x i64> %b, <2 x i64> undef, <2 x i32> zeroinitializer
%shift = shl <2 x i64> %a, %splat %shift = shl <2 x i64> %a, %splat
ret <2 x i64> %shift ret <2 x i64> %shift
} }
define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind { define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
; SSE2-LABEL: splatvar_shift_v4i32: ; SSE2-LABEL: splatvar_shift_v4i32:
; SSE2: # BB#0: ; SSE2: # BB#0:
; SSE2-NEXT: xorps %xmm2, %xmm2 ; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; SSE2-NEXT: pslld %xmm2, %xmm0 ; SSE2-NEXT: pslld %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: splatvar_shift_v4i32: ; SSE41-LABEL: splatvar_shift_v4i32:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: pxor %xmm2, %xmm2 ; SSE41-NEXT: pmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3,4,5,6,7] ; SSE41-NEXT: pslld %xmm1, %xmm0
; SSE41-NEXT: pslld %xmm2, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: splatvar_shift_v4i32: ; AVX-LABEL: splatvar_shift_v4i32:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; AVX-NEXT: vpslld %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpslld %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; XOP-LABEL: splatvar_shift_v4i32: ; XOP-LABEL: splatvar_shift_v4i32:
; XOP: # BB#0: ; XOP: # BB#0:
; XOP-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; XOP-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; XOP-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; XOP-NEXT: vpslld %xmm1, %xmm0, %xmm0 ; XOP-NEXT: vpslld %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; AVX512-LABEL: splatvar_shift_v4i32: ; AVX512-LABEL: splatvar_shift_v4i32:
; AVX512: ## BB#0: ; AVX512: ## BB#0:
; AVX512-NEXT: vxorps %xmm2, %xmm2, %xmm2 ; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX512-NEXT: vmovss {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3]
; AVX512-NEXT: vpslld %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpslld %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
; ;
; X32-SSE-LABEL: splatvar_shift_v4i32: ; X32-SSE-LABEL: splatvar_shift_v4i32:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: xorps %xmm2, %xmm2 ; X32-SSE-NEXT: xorps %xmm2, %xmm2
; X32-SSE-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] ; X32-SSE-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; X32-SSE-NEXT: pslld %xmm2, %xmm0 ; X32-SSE-NEXT: pslld %xmm2, %xmm0
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
%splat = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer %splat = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer
%shift = shl <4 x i32> %a, %splat %shift = shl <4 x i32> %a, %splat
ret <4 x i32> %shift ret <4 x i32> %shift
} }
define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind { define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
; SSE2-LABEL: splatvar_shift_v8i16: ; SSE2-LABEL: splatvar_shift_v8i16:
; SSE2: # BB#0: ; SSE2: # BB#0:
; SSE2-NEXT: pextrw $0, %xmm1, %eax ; SSE2-NEXT: pextrw $0, %xmm1, %eax
; SSE2-NEXT: movd %eax, %xmm1 ; SSE2-NEXT: movd %eax, %xmm1
; SSE2-NEXT: psllw %xmm1, %xmm0 ; SSE2-NEXT: psllw %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: splatvar_shift_v8i16: ; SSE41-LABEL: splatvar_shift_v8i16:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: pxor %xmm2, %xmm2 ; SSE41-NEXT: pmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3,4,5,6,7] ; SSE41-NEXT: psllw %xmm1, %xmm0
; SSE41-NEXT: psllw %xmm2, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: splatvar_shift_v8i16: ; AVX-LABEL: splatvar_shift_v8i16:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
; AVX-NEXT: vpsllw %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpsllw %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; XOP-LABEL: splatvar_shift_v8i16: ; XOP-LABEL: splatvar_shift_v8i16:
; XOP: # BB#0: ; XOP: # BB#0:
; XOP-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; XOP-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; XOP-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
; XOP-NEXT: vpsllw %xmm1, %xmm0, %xmm0 ; XOP-NEXT: vpsllw %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; AVX512-LABEL: splatvar_shift_v8i16: ; AVX512-LABEL: splatvar_shift_v8i16:
; AVX512: ## BB#0: ; AVX512: ## BB#0:
; AVX512-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX512-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
; AVX512-NEXT: vpsllw %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpsllw %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
; ;
; X32-SSE-LABEL: splatvar_shift_v8i16: ; X32-SSE-LABEL: splatvar_shift_v8i16:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pextrw $0, %xmm1, %eax ; X32-SSE-NEXT: pextrw $0, %xmm1, %eax
; X32-SSE-NEXT: movd %eax, %xmm1 ; X32-SSE-NEXT: movd %eax, %xmm1
; X32-SSE-NEXT: psllw %xmm1, %xmm0 ; X32-SSE-NEXT: psllw %xmm1, %xmm0
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llvm/trunk/test/CodeGen/X86/vector-shift-shl-256.ll

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%splat = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> zeroinitializer %splat = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> zeroinitializer
%shift = shl <4 x i64> %a, %splat %shift = shl <4 x i64> %a, %splat
ret <4 x i64> %shift ret <4 x i64> %shift
} }
define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind { define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
; AVX1-LABEL: splatvar_shift_v8i32: ; AVX1-LABEL: splatvar_shift_v8i32:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX1-NEXT: vpslld %xmm1, %xmm2, %xmm2 ; AVX1-NEXT: vpslld %xmm1, %xmm2, %xmm2
; AVX1-NEXT: vpslld %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpslld %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: splatvar_shift_v8i32: ; AVX2-LABEL: splatvar_shift_v8i32:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX2-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; AVX2-NEXT: vpslld %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: vpslld %xmm1, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; XOPAVX1-LABEL: splatvar_shift_v8i32: ; XOPAVX1-LABEL: splatvar_shift_v8i32:
; XOPAVX1: # BB#0: ; XOPAVX1: # BB#0:
; XOPAVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; XOPAVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; XOPAVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; XOPAVX1-NEXT: vpslld %xmm1, %xmm2, %xmm2 ; XOPAVX1-NEXT: vpslld %xmm1, %xmm2, %xmm2
; XOPAVX1-NEXT: vpslld %xmm1, %xmm0, %xmm0 ; XOPAVX1-NEXT: vpslld %xmm1, %xmm0, %xmm0
; XOPAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; XOPAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; XOPAVX1-NEXT: retq ; XOPAVX1-NEXT: retq
; ;
; XOPAVX2-LABEL: splatvar_shift_v8i32: ; XOPAVX2-LABEL: splatvar_shift_v8i32:
; XOPAVX2: # BB#0: ; XOPAVX2: # BB#0:
; XOPAVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; XOPAVX2-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; XOPAVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; XOPAVX2-NEXT: vpslld %xmm1, %ymm0, %ymm0 ; XOPAVX2-NEXT: vpslld %xmm1, %ymm0, %ymm0
; XOPAVX2-NEXT: retq ; XOPAVX2-NEXT: retq
; ;
; AVX512-LABEL: splatvar_shift_v8i32: ; AVX512-LABEL: splatvar_shift_v8i32:
; AVX512: ## BB#0: ; AVX512: ## BB#0:
; AVX512-NEXT: vxorps %xmm2, %xmm2, %xmm2 ; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX512-NEXT: vmovss {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3]
; AVX512-NEXT: vpslld %xmm1, %ymm0, %ymm0 ; AVX512-NEXT: vpslld %xmm1, %ymm0, %ymm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%splat = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> zeroinitializer %splat = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> zeroinitializer
%shift = shl <8 x i32> %a, %splat %shift = shl <8 x i32> %a, %splat
ret <8 x i32> %shift ret <8 x i32> %shift
} }
define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind { define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind {
; AVX1-LABEL: splatvar_shift_v16i16: ; AVX1-LABEL: splatvar_shift_v16i16:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpextrw $0, %xmm1, %eax ; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX1-NEXT: vmovd %eax, %xmm1
; AVX1-NEXT: vpsllw %xmm1, %xmm2, %xmm2 ; AVX1-NEXT: vpsllw %xmm1, %xmm2, %xmm2
; AVX1-NEXT: vpsllw %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpsllw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: splatvar_shift_v16i16: ; AVX2-LABEL: splatvar_shift_v16i16:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpextrw $0, %xmm1, %eax ; AVX2-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX2-NEXT: vmovd %eax, %xmm1
; AVX2-NEXT: vpsllw %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: vpsllw %xmm1, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; XOPAVX1-LABEL: splatvar_shift_v16i16: ; XOPAVX1-LABEL: splatvar_shift_v16i16:
; XOPAVX1: # BB#0: ; XOPAVX1: # BB#0:
; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; XOPAVX1-NEXT: vpextrw $0, %xmm1, %eax ; XOPAVX1-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; XOPAVX1-NEXT: vmovd %eax, %xmm1
; XOPAVX1-NEXT: vpsllw %xmm1, %xmm2, %xmm2 ; XOPAVX1-NEXT: vpsllw %xmm1, %xmm2, %xmm2
; XOPAVX1-NEXT: vpsllw %xmm1, %xmm0, %xmm0 ; XOPAVX1-NEXT: vpsllw %xmm1, %xmm0, %xmm0
; XOPAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; XOPAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; XOPAVX1-NEXT: retq ; XOPAVX1-NEXT: retq
; ;
; XOPAVX2-LABEL: splatvar_shift_v16i16: ; XOPAVX2-LABEL: splatvar_shift_v16i16:
; XOPAVX2: # BB#0: ; XOPAVX2: # BB#0:
; XOPAVX2-NEXT: vpextrw $0, %xmm1, %eax ; XOPAVX2-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; XOPAVX2-NEXT: vmovd %eax, %xmm1
; XOPAVX2-NEXT: vpsllw %xmm1, %ymm0, %ymm0 ; XOPAVX2-NEXT: vpsllw %xmm1, %ymm0, %ymm0
; XOPAVX2-NEXT: retq ; XOPAVX2-NEXT: retq
; ;
; AVX512-LABEL: splatvar_shift_v16i16: ; AVX512-LABEL: splatvar_shift_v16i16:
; AVX512: ## BB#0: ; AVX512: ## BB#0:
; AVX512-NEXT: vpextrw $0, %xmm1, %eax ; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX512-NEXT: vmovd %eax, %xmm1
; AVX512-NEXT: vpsllw %xmm1, %ymm0, %ymm0 ; AVX512-NEXT: vpsllw %xmm1, %ymm0, %ymm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%splat = shufflevector <16 x i16> %b, <16 x i16> undef, <16 x i32> zeroinitializer %splat = shufflevector <16 x i16> %b, <16 x i16> undef, <16 x i32> zeroinitializer
%shift = shl <16 x i16> %a, %splat %shift = shl <16 x i16> %a, %splat
ret <16 x i16> %shift ret <16 x i16> %shift
} }
define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
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llvm/trunk/test/CodeGen/X86/vector-shift-shl-512.ll

Show First 20 Lines • Show All 496 Lines • ▼ Show 20 Lines; ALL-NEXT: retq
%splat = shufflevector <8 x i64> %b, <8 x i64> undef, <8 x i32> zeroinitializer %splat = shufflevector <8 x i64> %b, <8 x i64> undef, <8 x i32> zeroinitializer
%shift = shl <8 x i64> %a, %splat %shift = shl <8 x i64> %a, %splat
ret <8 x i64> %shift ret <8 x i64> %shift
} }
define <16 x i32> @splatvar_shift_v16i32(<16 x i32> %a, <16 x i32> %b) nounwind { define <16 x i32> @splatvar_shift_v16i32(<16 x i32> %a, <16 x i32> %b) nounwind {
; ALL-LABEL: splatvar_shift_v16i32: ; ALL-LABEL: splatvar_shift_v16i32:
; ALL: ## BB#0: ; ALL: ## BB#0:
; ALL-NEXT: vxorps %xmm2, %xmm2, %xmm2 ; ALL-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; ALL-NEXT: vmovss {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3]
; ALL-NEXT: vpslld %xmm1, %zmm0, %zmm0 ; ALL-NEXT: vpslld %xmm1, %zmm0, %zmm0
; ALL-NEXT: retq ; ALL-NEXT: retq
%splat = shufflevector <16 x i32> %b, <16 x i32> undef, <16 x i32> zeroinitializer %splat = shufflevector <16 x i32> %b, <16 x i32> undef, <16 x i32> zeroinitializer
%shift = shl <16 x i32> %a, %splat %shift = shl <16 x i32> %a, %splat
ret <16 x i32> %shift ret <16 x i32> %shift
} }
define <32 x i16> @splatvar_shift_v32i16(<32 x i16> %a, <32 x i16> %b) nounwind { define <32 x i16> @splatvar_shift_v32i16(<32 x i16> %a, <32 x i16> %b) nounwind {
; AVX512DQ-LABEL: splatvar_shift_v32i16: ; AVX512DQ-LABEL: splatvar_shift_v32i16:
; AVX512DQ: ## BB#0: ; AVX512DQ: ## BB#0:
; AVX512DQ-NEXT: vpextrw $0, %xmm2, %eax ; AVX512DQ-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero
; AVX512DQ-NEXT: vmovd %eax, %xmm2
; AVX512DQ-NEXT: vpsllw %xmm2, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpsllw %xmm2, %ymm0, %ymm0
; AVX512DQ-NEXT: vpsllw %xmm2, %ymm1, %ymm1 ; AVX512DQ-NEXT: vpsllw %xmm2, %ymm1, %ymm1
; AVX512DQ-NEXT: retq ; AVX512DQ-NEXT: retq
; ;
; AVX512BW-LABEL: splatvar_shift_v32i16: ; AVX512BW-LABEL: splatvar_shift_v32i16:
; AVX512BW: ## BB#0: ; AVX512BW: ## BB#0:
; AVX512BW-NEXT: vpextrw $0, %xmm1, %eax ; AVX512BW-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX512BW-NEXT: vmovd %eax, %xmm1
; AVX512BW-NEXT: vpsllw %xmm1, %zmm0, %zmm0 ; AVX512BW-NEXT: vpsllw %xmm1, %zmm0, %zmm0
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
%splat = shufflevector <32 x i16> %b, <32 x i16> undef, <32 x i32> zeroinitializer %splat = shufflevector <32 x i16> %b, <32 x i16> undef, <32 x i32> zeroinitializer
%shift = shl <32 x i16> %a, %splat %shift = shl <32 x i16> %a, %splat
ret <32 x i16> %shift ret <32 x i16> %shift
} }
define <64 x i8> @splatvar_shift_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind { define <64 x i8> @splatvar_shift_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
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llvm/trunk/test/CodeGen/X86/vshift-4.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X32 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X64
; test vector shifts converted to proper SSE2 vector shifts when the shift ; test vector shifts converted to proper SSE2 vector shifts when the shift
; amounts are the same when using a shuffle splat. ; amounts are the same when using a shuffle splat.
define void @shift1a(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind { define void @shift1a(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind {
; X32-LABEL: shift1a: ; X32-LABEL: shift1a:
; X32: # BB#0: # %entry ; X32: # BB#0: # %entry
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movq {{.*#+}} xmm1 = xmm1[0],zero
; X32-NEXT: psllq %xmm1, %xmm0 ; X32-NEXT: psllq %xmm1, %xmm0
; X32-NEXT: movdqa %xmm0, (%eax) ; X32-NEXT: movdqa %xmm0, (%eax)
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: shift1a: ; X64-LABEL: shift1a:
; X64: # BB#0: # %entry ; X64: # BB#0: # %entry
; X64-NEXT: psllq %xmm1, %xmm0 ; X64-NEXT: psllq %xmm1, %xmm0
; X64-NEXT: movdqa %xmm0, (%rdi) ; X64-NEXT: movdqa %xmm0, (%rdi)
; X64-NEXT: retq ; X64-NEXT: retq
entry: entry:
%shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 0> %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%shl = shl <2 x i64> %val, %shamt %shl = shl <2 x i64> %val, %shamt
store <2 x i64> %shl, <2 x i64>* %dst store <2 x i64> %shl, <2 x i64>* %dst
ret void ret void
} }
; shift1b can't use a packed shift but can shift lanes separately and shuffle back together ; shift1b can't use a packed shift but can shift lanes separately and shuffle back together
define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind { define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind {
; X32-LABEL: shift1b: ; X32-LABEL: shift1b:
; X32: # BB#0: # %entry ; X32: # BB#0: # %entry
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1] ; X32-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
; X32-NEXT: movdqa %xmm0, %xmm3 ; X32-NEXT: movdqa %xmm0, %xmm3
; X32-NEXT: psllq %xmm2, %xmm3 ; X32-NEXT: psllq %xmm2, %xmm3
; X32-NEXT: movq {{.*#+}} xmm1 = xmm1[0],zero
; X32-NEXT: psllq %xmm1, %xmm0 ; X32-NEXT: psllq %xmm1, %xmm0
; X32-NEXT: movsd {{.*#+}} xmm3 = xmm0[0],xmm3[1] ; X32-NEXT: movsd {{.*#+}} xmm3 = xmm0[0],xmm3[1]
; X32-NEXT: movapd %xmm3, (%eax) ; X32-NEXT: movapd %xmm3, (%eax)
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: shift1b: ; X64-LABEL: shift1b:
; X64: # BB#0: # %entry ; X64: # BB#0: # %entry
; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1] ; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
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