Improve mul combine for negative multiplayer (2^c - 1)

[m_zuckerman]

Summary

This function improves the mul instruction combine function (combineMul)
by adding new layer of logic.
In this patch, we are adding the ability to fold (mul x, -((1 << c) -1))
or (mul x, -((1 << c) +1)) into (neg(X << c) -x) or (neg((x << c) + x) respective.

[igorb]

lib/Target/X86/X86ISelLowering.cpp

28880

does NumSign * SignMulAmt == MulAmt, or i missing something ?

28888

this is common code for the both cases . can we put it after if/else ?
if (NumSign == -1 && NewMul) ...

test/CodeGen/X86/imul.ll

175

Sorry, i can't understand the test output. Could you please auto-generate the CHECKS ?

[m_zuckerman]

lib/Target/X86/X86ISelLowering.cpp

28880

Yes mine is sext will the MulAmt is zext

[igorb]

LGTM

[efriedma]

How did this get merged without any performance data? It isn't obvious this is a good idea.

[m_zuckerman]

Hi Eli,

We tested the patch with internal performance tests.
If you have test/suite/benchmark that my patch bring down, please share them with me.

Regards,
Michael Zuckerman

[efriedma]

I don't have any specific issue with this patch (I don't do x86 benchmarking), but it would be a good idea to have some sort of record of what this is actually improving; if someone revisits this code in the future, they won't have access to Intel-internal benchmark numbers.

lib/Target/X86/X86ISelLowering.cpp

if (isPowerOf2_64(MulAmt2))
       NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
                            DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
     else
       NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
                            DAG.getConstant(MulAmt2, DL, VT));
   }
 
   if (!NewMul) {
-    assert(MulAmt != 0 && MulAmt != (VT == MVT::i64 ? UINT64_MAX : UINT32_MAX)
-           && "Both cases that could cause potential overflows should have "
-              "already been handled.");
-    if (isPowerOf2_64(MulAmt - 1))
+    assert(MulAmt != 0 &&
+           MulAmt != (VT == MVT::i64 ? UINT64_MAX : UINT32_MAX) &&
+           "Both cases that could cause potential overflows should have "
+    int64_t SignMulAmt = C->getSExtValue();
+    if ((SignMulAmt != INT64_MIN) && (SignMulAmt != INT64_MAX) &&
+        (SignMulAmt != -INT64_MAX)) {
+      int NumSign = SignMulAmt > 0 ? 1 : -1;
+      if (isPowerOf2_64(NumSign * SignMulAmt - 1)) {
         // (mul x, 2^N + 1) => (add (shl x, N), x)
-      NewMul = DAG.getNode(ISD::ADD, DL, VT, N->getOperand(0),
-                                DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
-                                DAG.getConstant(Log2_64(MulAmt - 1), DL,
+        NewMul = DAG.getNode(
+            ISD::ADD, DL, VT, N->getOperand(0),
+                        DAG.getConstant(Log2_64(NumSign * SignMulAmt - 1), DL,
                                         MVT::i8)));
-
-    else if (isPowerOf2_64(MulAmt + 1))
+        // To negate, subtract the number from zero
+        if (NumSign == -1)
+          NewMul =
+              DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), NewMul);
+      } else if (isPowerOf2_64(NumSign * SignMulAmt + 1)) {
         // (mul x, 2^N - 1) => (sub (shl x, N), x)
-      NewMul = DAG.getNode(ISD::SUB, DL, VT, DAG.getNode(ISD::SHL, DL, VT,
-                                N->getOperand(0),
-                                DAG.getConstant(Log2_64(MulAmt + 1),
-                                DL, MVT::i8)), N->getOperand(0));
+        NewMul = DAG.getNode(
+            ISD::SUB, DL, VT,
+            DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
+                        DAG.getConstant(Log2_64(NumSign * SignMulAmt + 1), DL,
+                                        MVT::i8)),
+            N->getOperand(0));
+        // To negate, subtract the number from zero
+        if (NumSign == -1)
+          NewMul =
+              DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), NewMul);
+      }
+    }
   }
 
   if (NewMul)
     // Do not add new nodes to DAG combiner worklist.
     DCI.CombineTo(N, NewMul, false);
 
   return SDValue();
 }

test/CodeGen/X86/imul.ll

 
 define i64 @mul18446744073709551615_64(i64 %A) {
 ; X64-LABEL: mul18446744073709551615_64:
 ; X64: negq %rdi
 ; X64-NEXT: movq  %rdi, %rax
     %mul = mul i64 %A, 18446744073709551615
     ret i64 %mul
 }
+  
+define i32 @test(i32 %a) {
+entry:
+  %tmp3 = mul i32 %a, 31
+;   CHECK-LABEL: test:
+; CHECK-NOT: imul 
+;   CHECK: shll 
+;   CHECK-NEXT: sub
+  ret i32 %tmp3
+}
+
+define i32 @test1(i32 %a) {
+entry:
+  %tmp3 = mul i32 %a, -31
+;   CHECK-LABEL: test1:
+; CHECK-NOT: imul 
+;   CHECK: shll 
+;   CHECK-NEXT: sub
+;   CHECK-NEXT: negl
+  ret i32 %tmp3
+}
+
+
+define i32 @test2(i32 %a) {
+entry:
+  %tmp3 = mul i32 %a, 33
+;   CHECK-LABEL: test2:
+; CHECK-NOT: imul 
+;   CHECK: shll 
+;   CHECK-NEXT: leal
+  ret i32 %tmp3
+}
+
+define i32 @test3(i32 %a) {
+entry:
+  %tmp3 = mul i32 %a, -33
+;   CHECK-LABEL: test3:
+; CHECK-NOT: imul 
+;   CHECK: shll 
+;   CHECK-NEXT: leal
+;   CHECK-NEXT: negl
+  ret i32 %tmp3
+}
+
+define i64 @test4(i64 %a) {
+entry:
+  %tmp3 = mul i64 %a, 31
+;   CHECK-LABEL: test4:
+; CHECK-NOT: imul 
+;   CHECK: shlq 
+;   CHECK-NEXT: sub
+  ret i64 %tmp3
+}
+
+define i64 @test5(i64 %a) {
+entry:
+  %tmp3 = mul i64 %a, -31
+;   CHECK-LABEL: test5:
+; CHECK-NOT: imul 
+;   CHECK: shlq 
+;   CHECK-NEXT: sub
+;   CHECK-NEXT: negq
+  ret i64 %tmp3
+}
+
+
+define i64 @test6(i64 %a) {
+entry:
+  %tmp3 = mul i64 %a, 33
+;   CHECK-LABEL: test6:
+; CHECK-NOT: imul 
+;   CHECK: shlq 
+;   CHECK-NEXT: leaq
+  ret i64 %tmp3
+}
+
+define i64 @test7(i64 %a) {
+entry:
+  %tmp3 = mul i64 %a, -33
+;   CHECK-LABEL: test7:
+; CHECK-NOT: imul 
+;   CHECK: shlq 
+;   CHECK-NEXT: leaq
+;   CHECK-NEXT: negq
+  ret i64 %tmp3
+}
+
+define i64 @testOverflow(i64 %a) {
+entry:
+  %tmp3 = mul i64 %a, 9223372036854775807
+;   CHECK-LABEL: testOverflow:
+; CHECK-NOT: shl
+  ret i64 %tmp3
+}