[X86][FastISel] Fix lowering of overflow result on AVX512 targets

[zvi]

Summary

Fix a case where the overflow value of type i1, which is legal on AVX512, was assigned to a VK1 register class.
We always want this value to be assigned to a GPR since the overflow return value is lowered to a SETO instruction.

Fixes pr30981.

[qcolombet]

LGTM

lib/Target/X86/X86FastISel.cpp

2774

This could be in a separate NFC patch.

2884

Add a comment on why GR8 is the right class at this point.

[zvi]

lib/Target/X86/X86FastISel.cpp

2774

Sure

2884

Ok

[zvi]

r286958

lib/Target/X86/X86FastISel.cpp

bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
   case Intrinsic::usub_with_overflow:
   case Intrinsic::smul_with_overflow:
   case Intrinsic::umul_with_overflow: {
     // This implements the basic lowering of the xalu with overflow intrinsics
     // into add/sub/mul followed by either seto or setb.
     const Function *Callee = II->getCalledFunction();
     auto *Ty = cast<StructType>(Callee->getReturnType());
     Type *RetTy = Ty->getTypeAtIndex(0U);
-    Type *CondTy = Ty->getTypeAtIndex(1);
+    assert(Ty->getTypeAtIndex(1)->isIntegerTy() &&
+           Ty->getTypeAtIndex(1)->getScalarSizeInBits() == 1 &&
+           "Overflow value expected to be an i1");
 
     MVT VT;
     if (!isTypeLegal(RetTy, VT))
       return false;
 
     if (VT < MVT::i8 || VT > MVT::i64)
       return false;
 
if (BaseOpc == X86ISD::UMUL && !ResultReg) {
         ResultReg = fastEmitInst_rr(MULOpc[VT.SimpleTy-MVT::i8],
                                     TLI.getRegClassFor(VT), LHSReg, LHSIsKill,
                                     RHSReg, RHSIsKill);
     }
 
     if (!ResultReg)
       return false;
 
-    unsigned ResultReg2 = FuncInfo.CreateRegs(CondTy);
+    unsigned ResultReg2 = createResultReg(&X86::GR8RegClass);
     assert((ResultReg+1) == ResultReg2 && "Nonconsecutive result registers.");
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CondOpc),
             ResultReg2);
 
     updateValueMap(II, ResultReg, 2);
     return true;
   }
   case Intrinsic::x86_sse_cvttss2si:

test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll

 ; radr://6772169
 ; RUN: llc < %s -fast-isel
 ; PR30981
 ; RUN: llc < %s -O0 -mcpu=x86-64 -mattr=+avx512f | FileCheck %s
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-apple-darwin10"
   %0 = type { i32, i1 }   ; type %0
 
 declare %0 @llvm.sadd.with.overflow.i32(i32, i32) nounwind
 
 define fastcc i32 @test() nounwind {
 entry:
-; CHECK-LABEL: _test:
-; CHECK:      ## BB#0:
-; CHECK-NEXT: movl    $1, %eax
-; CHECK-NEXT: addl    $0, %eax
-; CHECK-NEXT: seto    %k0
-; CHECK-NEXT: movl    %eax, -4(%rsp)          ## 4-byte Spill
-; CHECK-NEXT: kmovw   %k0, -6(%rsp)           ## 2-byte Spill
-; CHECK-NEXT: jo      LBB0_2
+; CHECK-LABEL: test:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    addl $0, %eax
+; CHECK-NEXT:    seto %cl
+; CHECK-NEXT:    movl %eax, -{{[0-9]+}}(%rsp) ## 4-byte Spill
+; CHECK-NEXT:    movb %cl, -{{[0-9]+}}(%rsp) ## 1-byte Spill
+; CHECK-NEXT:    jo LBB0_2
   %tmp1 = call %0 @llvm.sadd.with.overflow.i32(i32 1, i32 0)
   %tmp2 = extractvalue %0 %tmp1, 1
   br i1 %tmp2, label %.backedge, label %BB3
 
 BB3:
   %tmp4 = extractvalue %0 %tmp1, 0
   br label %.backedge
 
 .backedge:
   ret i32 0
 }