MIRParser: Add support for parsing vreg reg alloc hints

[MatzeB]

LGTM.

lib/CodeGen/MIRParser/MIParser.h

 /// Return true if an error occurred.
 bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src,
                               SMDiagnostic &Error);
 
 bool parseMBBReference(PerFunctionMIParsingState &PFS,
                        MachineBasicBlock *&MBB, StringRef Src,
                        SMDiagnostic &Error);
 
+bool parseRegisterReference(PerFunctionMIParsingState &PFS,
+                            unsigned &Reg, StringRef Src,
+                            SMDiagnostic &Error);
+
 bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, unsigned &Reg,
                                  StringRef Src, SMDiagnostic &Error);
 
 bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS,
                                    VRegInfo *&Info, StringRef Src,
                                    SMDiagnostic &Error);
 
 bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI,
                                StringRef Src, SMDiagnostic &Error);
 
 bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src,
                  SMDiagnostic &Error);
 
 } // end namespace llvm
 
 #endif

lib/CodeGen/MIRParser/MIParser.cpp

public:
 
   bool
   parseBasicBlockDefinitions(DenseMap<unsigned, MachineBasicBlock *> &MBBSlots);
   bool parseBasicBlocks();
   bool parse(MachineInstr *&MI);
   bool parseStandaloneMBB(MachineBasicBlock *&MBB);
   bool parseStandaloneNamedRegister(unsigned &Reg);
   bool parseStandaloneVirtualRegister(VRegInfo *&Info);
+  bool parseStandaloneRegister(unsigned &Reg);
   bool parseStandaloneStackObject(int &FI);
   bool parseStandaloneMDNode(MDNode *&Node);
 
   bool
   parseBasicBlockDefinition(DenseMap<unsigned, MachineBasicBlock *> &MBBSlots);
   bool parseBasicBlock(MachineBasicBlock &MBB);
   bool parseBasicBlockLiveins(MachineBasicBlock &MBB);
   bool parseBasicBlockSuccessors(MachineBasicBlock &MBB);
bool MIParser::parseStandaloneVirtualRegister(VRegInfo *&Info) {
   if (parseVirtualRegister(Info))
     return true;
   lex();
   if (Token.isNot(MIToken::Eof))
     return error("expected end of string after the register reference");
   return false;
 }
 
+bool MIParser::parseStandaloneRegister(unsigned &Reg) {
+  lex();
+  if (Token.isNot(MIToken::NamedRegister) &&
+      Token.isNot(MIToken::VirtualRegister))
+    return error("expected either a named or virtual register");
+
+  VRegInfo *Info;
+  if (parseRegister(Reg, Info))
+    return true;
+
+  lex();
+  if (Token.isNot(MIToken::Eof))
+    return error("expected end of string after the register reference");
+  return false;
+}
+
 bool MIParser::parseStandaloneStackObject(int &FI) {
   lex();
   if (Token.isNot(MIToken::StackObject))
     return error("expected a stack object");
   if (parseStackFrameIndex(FI))
     return true;
   if (Token.isNot(MIToken::Eof))
     return error("expected end of string after the stack object reference");

 }
 
 bool llvm::parseMBBReference(PerFunctionMIParsingState &PFS,
                              MachineBasicBlock *&MBB, StringRef Src,
                              SMDiagnostic &Error) {
   return MIParser(PFS, Error, Src).parseStandaloneMBB(MBB);
 }
 
+bool llvm::parseRegisterReference(PerFunctionMIParsingState &PFS,
+                                  unsigned &Reg, StringRef Src,
+                                  SMDiagnostic &Error) {
+  return MIParser(PFS, Error, Src).parseStandaloneRegister(Reg);
+}
+
 bool llvm::parseNamedRegisterReference(PerFunctionMIParsingState &PFS,
                                        unsigned &Reg, StringRef Src,
                                        SMDiagnostic &Error) {
   return MIParser(PFS, Error, Src).parseStandaloneNamedRegister(Reg);
 }
 
 bool llvm::parseVirtualRegisterReference(PerFunctionMIParsingState &PFS,
                                          VRegInfo *&Info, StringRef Src,

lib/CodeGen/MIRParser/MIRParser.cpp

if (StringRef(VReg.Class.Value).equals("_")) {
         Info.D.RegBank = RegBank;
       }
     }
 
     if (!VReg.PreferredRegister.Value.empty()) {
       if (Info.Kind != VRegInfo::NORMAL)
         return error(VReg.Class.SourceRange.Start,
               Twine("preferred register can only be set for normal vregs"));
-      if (parseNamedRegisterReference(PFS, Info.PreferredReg,
-                                      VReg.PreferredRegister.Value, Error))
+
+      if (parseRegisterReference(PFS, Info.PreferredReg,
         return error(Error, VReg.PreferredRegister.SourceRange);
     }
   }
 
   // Parse the liveins.
   for (const auto &LiveIn : YamlMF.LiveIns) {
     unsigned Reg = 0;
     if (parseNamedRegisterReference(PFS, Reg, LiveIn.Register.Value, Error))

test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir

-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: llc -march=x86-64 -run-pass none -o - %s 2>&1 | FileCheck %s
 
 --- |
 
   define i32 @test(i32 %a, i32 %b) {
   body:
     %c = mul i32 %a, %b
     ret i32 %c
   }
 
 ...
 ---
 name:            test
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
-  # CHECK: [[@LINE+1]]:48: expected a named register
+  # CHECK: - { id: 1, class: gr32, preferred-register: '%0' }
+  # CHECK: - { id: 2, class: gr32, preferred-register: '%edi' }
   - { id: 1, class: gr32, preferred-register: '%0' }
   - { id: 2, class: gr32, preferred-register: '%edi' }
 body: |
   bb.0.body:
     liveins: %edi, %esi
 
     %1 = COPY %esi
     %2 = COPY %edi
     %2 = IMUL32rr %2, %1, implicit-def dead %eflags
     %eax = COPY %2
     RETQ killed %eax
 ...