[LLD][PPC] Implement R_PPC_REL24 and R_PPC_REL32 relocations

[jackoalan]

Summary

This enables LLD to relocate PC-relative R_PPC_REL32 and R_PPC_REL24 types (as used in bl instructions).

[ruiu]

Can you add a test?

[jackoalan]

Ok, I've appended a simple test for REL24 in ppc-relocs.s:

.align 2
.section .R_PPC_REL24,"ax",@progbits
.globl .FR_PPC_REL24
.FR_PPC_REL24:
  b .Lfoox
.section .R_PPC_REL24_2,"ax",@progbits
.Lfoox:

# CHECK: Disassembly of section .R_PPC_REL24:
# CHECK: .FR_PPC_REL24:
# CHECK:    11014:       48 00 00 04     b .+4

That passes as expected, but I'm not sure how to emit a REL32 using assembler directives. I implemented REL32 because the .eh_frame section needs it when linking C++ (presumably to reference the functions being unwound).

If anyone knows how to do it with assembler directives or symbol variants, I'll write that test as well.

[ruiu]

I'm not a PowerPC expert, but maybe something like this?

.global foo
.section .R_PPC_REL32,"a"
  .quad foobar

[ruiu]

Sorry, I mean

.global foo
.section .R_PPC_REL32,"a"
  .quad foo

[jackoalan]

That ends up emitting R_PPC_ADDR32 (absolute relocation, which also needs to be implemented).

I managed to get it emitting using CFI directives (i.e. .cfi_startproc and .cfi_endproc), but I'm not entirely certain now that particular relocation usage should function.

[jackoalan]

This adds a test for REL24.

REL32 conformance uncertain right now. Need assembler directive, or how to validate .cfi* directives that emit REL32.

[ruiu]

LGTM for now. Please add a test for REL32 in a future patch.

[jackoalan]

Since ADDR32 was a trivial relocation for the last diff, this test is added to validate

[ruiu]

Please submit the previous patch and send the new change as a new patch.

[jackoalan]

Just to clarify, update diff to include *just* REL24/REL32, then submit ADDR32 standalone?

[ruiu]

I mean I requested you submit the patch when I LGTMed, and then send me another patch to add ADDR32 support. (You usually want to submit a patch as soon as LGTMed and then make new features as new patches, instead of adding new code to an unsubmitted change. )

[jackoalan]

Restore LGTM'd patch

[jackoalan]

Ensure patch contents reflects title (no ADDR32)

[ruiu]

Do you have a commit access? If so, please commit.

[jackoalan]

All I've set up is the Phabricator access, no commit privileges to my knowledge

[ruiu]

Ah, I was thinking that you had a commit access but for some reason didn't submit all these changes. I'll do that for you.

[ruiu]

Committed as r285719.

ELF/Target.cpp

 using namespace llvm::ELF;
 
 namespace lld {
 namespace elf {
 
 TargetInfo *Target;
 
 static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); }
+static void or32be(uint8_t *P, int32_t V) { write32be(P, read32be(P) | V); }
 
 StringRef getRelName(uint32_t Type) {
   return getELFRelocationTypeName(Config->EMachine, Type);
 }
 
 template <unsigned N> static void checkInt(int64_t V, uint32_t Type) {
   if (!isInt<N>(V))
     error("relocation " + getRelName(Type) + " out of range");
void PPCTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
                                 uint64_t Val) const {
   switch (Type) {
   case R_PPC_ADDR16_HA:
     write16be(Loc, applyPPCHa(Val));
     break;
   case R_PPC_ADDR16_LO:
     write16be(Loc, applyPPCLo(Val));
     break;
+  case R_PPC_REL24:
+    or32be(Loc, Val & 0x3FFFFFC);
+    break;
+  case R_PPC_REL32:
+    write32be(Loc, Val);
+    break;
   default:
     fatal("unrecognized reloc " + Twine(Type));
   }
 }
 
 RelExpr PPCTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
+  switch (Type) {
+  case R_PPC_REL24:
+  case R_PPC_REL32:
+    return R_PC;
+  default:
     return R_ABS;
   }
+}
 
 PPC64TargetInfo::PPC64TargetInfo() {
   PltRel = GotRel = R_PPC64_GLOB_DAT;
   RelativeRel = R_PPC64_RELATIVE;
   GotEntrySize = 8;
   GotPltEntrySize = 8;
   PltEntrySize = 32;
   PltHeaderSize = 0;

test/ELF/ppc-relocs.s

mystr:
   .asciz "blah"
   len = . - mystr
 
 # CHECK: Disassembly of section .R_PPC_ADDR16_LO:
 # CHECK: .R_PPC_ADDR16_LO:
 # CHECK:    11008:       38 84 10 04     addi 4, 4, 4100
 # CHECK: mystr:
 # CHECK:    1100c:       62 6c 61 68     ori 12, 19, 24936
+
+.align  2
+.section .R_PPC_REL24,"ax",@progbits
+.globl .FR_PPC_REL24
+.FR_PPC_REL24:
+  b .Lfoox
+.section .R_PPC_REL24_2,"ax",@progbits
+.Lfoox:
+
+# CHECK: Disassembly of section .R_PPC_REL24:
+# CHECK: .FR_PPC_REL24:
+# CHECK:    11014:       48 00 00 04     b .+4