This patch adds _InterlockedCompareExchangePointer to Intrin.h. It has only been made available when x86_64 similar to MSVC Intrin.h. Please review.
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Updated patch to include an implementation of __faststorefence based on cl assembly output.
Adding people that might want to review this change and commit it for me if it's acceptable. :)
Thanks, looks good, I'll commit it.
Looks like we were missing some of the declaration stubs for intrin.h, so
Eric went ahead and added the rest in r199992 and r200061. Feel free to
send more implementations.
lib/Headers/Intrin.h | ||
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783 | I think this needs to have a memory constraint to avoid reordering non-volatile loads and stores across it. |
lib/Headers/Intrin.h | ||
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783 | This instruction reads a memory address, or's it with the constant 0, and writes it back to the same location with the lock prefix. That's read-modify-write with lock prefix, and I believe the AMD and Intel manuals state that this should be enough. I can provide references if you like. It's also the same instruction emitted by MSVC. | |
783 | Alternatively, we could use sfence here. Are you a also looking to prevent the compiler from re-ordering this instruction? Will it do that? |
lib/Headers/Intrin.h | ||
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783 | I meant it needs to have a gcc inline asm style "memory" constraint, like so: __asm__ volatile("lock orq $0, (%%rsp)" : : : "memory"); GCC doesn't parse inline assembly, so it needs the user to carefully spell out the constraints on scheduling. Clang follows that model for gcc-style inline asm. |
You are correct, and I think the change was already committed with that fix
applied. Thank you. I was just trying to mark the review as "finished" or
"accepted". Please excuse my unfamiliarity with Confabulator's workflow.
I think this needs to have a memory constraint to avoid reordering non-volatile loads and stores across it.