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Differential D25672

[mips] Fix sync instruction definition
ClosedPublic

Authored by sdardis on Oct 17 2016, 6:11 AM.

Details

Reviewers
vkalintiris
Commits
rGc4463c942c09: [mips] Fix sync instruction definition
rL284483: [mips] Fix sync instruction definition
Summary

The 'sync' instruction for MIPS was defined in MIPS-II as taking no operands.
MIPS32 extended the define of 'sync' as taking an optional unsigned 5 bit
immediate.

This patch correct the definition of sync so that it is accepted with an
operand of 0 or no operand for MIPS-II to MIPS-V, and a 5 bit unsigned
immediate for MIPS32 and later revisions.

Additionally a clear error is given when the MIPS32 version of sync is
used when targeting pre MIPS32.

This partially resolves PR/30714.

Thanks to Daniel Sanders for reporting this issue!

Diff Detail

Event Timeline

sdardis updated this revision to Diff 74833.Oct 17 2016, 6:11 AM
sdardis retitled this revision from to [mips] Fix sync instruction definition.
sdardis updated this object.
sdardis added a reviewer: vkalintiris.
sdardis set the repository for this revision to rL LLVM.
sdardis added a subscriber: llvm-commits.
Herald edited edge metadata. · View Herald TranscriptOct 17 2016, 6:11 AM
vkalintiris accepted this revision.Oct 18 2016, 7:18 AM
vkalintiris edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Oct 18 2016, 7:18 AM
Closed by commit rL284483: [mips] Fix sync instruction definition (authored by sdardis). · Explain WhyOct 18 2016, 7:51 AM
This revision was automatically updated to reflect the committed changes.
sdardis added a comment.Oct 18 2016, 7:53 AM

Thanks.

Revision Contents

PathSize
lib/
Target/
Mips/
AsmParser/
7 lines
3 lines
test/
MC/
Mips/
mips2/
3 lines
1 line
mips3/
3 lines
1 line
mips4/
3 lines
1 line
mips5/
3 lines
1 line

Diff 74833

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Show First 20 Lines • Show All 395 Lines • ▼ Show 20 Lines#include "MipsGenAsmMatcher.inc"
} }
public: public:
enum MipsMatchResultTy { enum MipsMatchResultTy {
Match_RequiresDifferentSrcAndDst = FIRST_TARGET_MATCH_RESULT_TY, Match_RequiresDifferentSrcAndDst = FIRST_TARGET_MATCH_RESULT_TY,
Match_RequiresDifferentOperands, Match_RequiresDifferentOperands,
Match_RequiresNoZeroRegister, Match_RequiresNoZeroRegister,
Match_RequiresSameSrcAndDst, Match_RequiresSameSrcAndDst,
Match_NonZeroOperandForSync,
#define GET_OPERAND_DIAGNOSTIC_TYPES #define GET_OPERAND_DIAGNOSTIC_TYPES
#include "MipsGenAsmMatcher.inc" #include "MipsGenAsmMatcher.inc"
#undef GET_OPERAND_DIAGNOSTIC_TYPES #undef GET_OPERAND_DIAGNOSTIC_TYPES
}; };
MipsAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser, MipsAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
const MCInstrInfo &MII, const MCTargetOptions &Options) const MCInstrInfo &MII, const MCTargetOptions &Options)
: MCTargetAsmParser(Options, sti), : MCTargetAsmParser(Options, sti),
▲ Show 20 Lines • Show All 3,443 Lines • ▼ Show 20 Lines case Mips::JALRC_MMR6:
if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg())
return Match_RequiresDifferentSrcAndDst; return Match_RequiresDifferentSrcAndDst;
return Match_Success; return Match_Success;
case Mips::LWP_MM: case Mips::LWP_MM:
case Mips::LWP_MMR6: case Mips::LWP_MMR6:
if (Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) if (Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg())
return Match_RequiresDifferentSrcAndDst; return Match_RequiresDifferentSrcAndDst;
return Match_Success; return Match_Success;
case Mips::SYNC:
if (Inst.getOperand(0).getImm() != 0 && !hasMips32())
return Match_NonZeroOperandForSync;
return Match_Success;
// As described the MIPSR6 spec, the compact branches that compare registers // As described the MIPSR6 spec, the compact branches that compare registers
// must: // must:
// a) Not use the zero register. // a) Not use the zero register.
// b) Not use the same register twice. // b) Not use the same register twice.
// c) rs < rt for bnec, beqc. // c) rs < rt for bnec, beqc.
// NB: For this case, the encoding will swap the operands as their // NB: For this case, the encoding will swap the operands as their
// ordering doesn't matter. GAS performs this transformation too. // ordering doesn't matter. GAS performs this transformation too.
// Hence, that constraint does not have to be enforced. // Hence, that constraint does not have to be enforced.
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines if (ErrorInfo != ~0ULL) {
ErrorLoc = Operands[ErrorInfo]->getStartLoc(); ErrorLoc = Operands[ErrorInfo]->getStartLoc();
if (ErrorLoc == SMLoc()) if (ErrorLoc == SMLoc())
ErrorLoc = IDLoc; ErrorLoc = IDLoc;
} }
return Error(ErrorLoc, "invalid operand for instruction"); return Error(ErrorLoc, "invalid operand for instruction");
} }
case Match_NonZeroOperandForSync:
return Error(IDLoc, "s-type must be zero or unspecified for pre-MIPS32 ISAs");
case Match_MnemonicFail: case Match_MnemonicFail:
return Error(IDLoc, "invalid instruction"); return Error(IDLoc, "invalid instruction");
case Match_RequiresDifferentSrcAndDst: case Match_RequiresDifferentSrcAndDst:
return Error(IDLoc, "source and destination must be different"); return Error(IDLoc, "source and destination must be different");
case Match_RequiresDifferentOperands: case Match_RequiresDifferentOperands:
return Error(IDLoc, "registers must be different"); return Error(IDLoc, "registers must be different");
case Match_RequiresNoZeroRegister: case Match_RequiresNoZeroRegister:
return Error(IDLoc, "invalid operand ($zero) for instruction"); return Error(IDLoc, "invalid operand ($zero) for instruction");
▲ Show 20 Lines • Show All 2,523 Lines • Show Last 20 Lines

lib/Target/Mips/MipsInstrInfo.td

Show First 20 Lines • Show All 1,865 Lines • ▼ Show 20 Lineslet DecoderNamespace = "COP3_" in {
def SWC3 : SW_FT3<"swc3", COP3Opnd, II_SWC3, store>, LW_FM<0x3b>; def SWC3 : SW_FT3<"swc3", COP3Opnd, II_SWC3, store>, LW_FM<0x3b>;
def LDC3 : LW_FT3<"ldc3", COP3Opnd, II_LDC3, load>, LW_FM<0x37>, def LDC3 : LW_FT3<"ldc3", COP3Opnd, II_LDC3, load>, LW_FM<0x37>,
ISA_MIPS2; ISA_MIPS2;
def SDC3 : SW_FT3<"sdc3", COP3Opnd, II_SDC3, store>, LW_FM<0x3f>, def SDC3 : SW_FT3<"sdc3", COP3Opnd, II_SDC3, store>, LW_FM<0x3f>,
ISA_MIPS2; ISA_MIPS2;
} }
} }
def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS2;
ISA_MIPS32;
def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2; def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm10, II_TEQ>, TEQ_FM<0x34>, ISA_MIPS2; def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm10, II_TEQ>, TEQ_FM<0x34>, ISA_MIPS2;
def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm10, II_TGE>, TEQ_FM<0x30>, ISA_MIPS2; def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm10, II_TGE>, TEQ_FM<0x30>, ISA_MIPS2;
def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm10, II_TGEU>, TEQ_FM<0x31>, ISA_MIPS2; def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm10, II_TGEU>, TEQ_FM<0x31>, ISA_MIPS2;
def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm10, II_TLT>, TEQ_FM<0x32>, ISA_MIPS2; def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm10, II_TLT>, TEQ_FM<0x32>, ISA_MIPS2;
def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm10, II_TLTU>, TEQ_FM<0x33>, ISA_MIPS2; def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm10, II_TLTU>, TEQ_FM<0x33>, ISA_MIPS2;
▲ Show 20 Lines • Show All 941 Lines • Show Last 20 Lines

test/MC/Mips/mips2/invalid-mips32.s

Show All 34 Lines# RUN: FileCheck %s < %t1
movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
msubu $15,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled msubu $15,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mtc0 $9,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mtc0 $9,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: s-type must be zero or unspecified for pre-MIPS32 ISAs
sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

test/MC/Mips/mips2/valid.s

Show First 20 Lines • Show All 153 Lines • ▼ Show 20 Linesa:
subu $sp,$s6,$s6 subu $sp,$s6,$s6
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swc3 $10,-32265($k0) swc3 $10,-32265($k0)
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
sync 0 # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
teqi $s5,-17504 teqi $s5,-17504
tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30]
tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30]
tgei $s1,5025 tgei $s1,5025
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

test/MC/Mips/mips3/invalid-mips32.s

# Instructions that are invalid # Instructions that are invalid
# #
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips3 \ # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips3 \
# RUN: 2>%t1 # RUN: 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.set noat .set noat
sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: s-type must be zero or unspecified for pre-MIPS32 ISAs
sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

test/MC/Mips/mips3/valid.s

Show First 20 Lines • Show All 217 Lines • ▼ Show 20 Linesa:
sub.s $f23,$f22,$f22 sub.s $f23,$f22,$f22
subu $sp,$s6,$s6 subu $sp,$s6,$s6
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
sync 0 # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
teqi $s5,-17504 teqi $s5,-17504
tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30]
tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30]
tgei $s1,5025 tgei $s1,5025
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

test/MC/Mips/mips4/invalid-mips32.s

# Instructions that are invalid # Instructions that are invalid
# #
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips4 \ # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips4 \
# RUN: 2>%t1 # RUN: 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.set noat .set noat
sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: s-type must be zero or unspecified for pre-MIPS32 ISAs
sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

test/MC/Mips/mips4/valid.s

Show First 20 Lines • Show All 250 Lines • ▼ Show 20 Linesa:
subu $sp,$s6,$s6 subu $sp,$s6,$s6
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
swxc1 $f19,$12($k0) swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
sync 0 # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
teqi $s5,-17504 teqi $s5,-17504
tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30]
tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30]
tgei $s1,5025 tgei $s1,5025
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

test/MC/Mips/mips5/invalid-mips32.s

# Instructions that are invalid # Instructions that are invalid
# #
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips5 \ # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips5 \
# RUN: 2>%t1 # RUN: 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.set noat .set noat
sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: s-type must be zero or unspecified for pre-MIPS32 ISAs
sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

test/MC/Mips/mips5/valid.s

Show First 20 Lines • Show All 252 Lines • ▼ Show 20 Linesa:
suxc1 $f12,$k1($13) suxc1 $f12,$k1($13)
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
swxc1 $f19,$12($k0) swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
sync 0 # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
teqi $s5,-17504 teqi $s5,-17504
tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30]
tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30]
tgei $s1,5025 tgei $s1,5025
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines