Handle lane masks in LivePhysRegs when adding live-ins

[kparzysz]

Summary

LivePhysRegs needs to take lane masks into account when adding live-ins.

Now I can finally have a testcase for this. :)

[MatzeB]

LGTM, thanks

include/llvm/CodeGen/LivePhysRegs.h

public:
   const_iterator begin() const { return LiveRegs.begin(); }
   const_iterator end() const { return LiveRegs.end(); }
 
   /// \brief Prints the currently live registers to @p OS.
   void print(raw_ostream &OS) const;
 
   /// \brief Dumps the currently live registers to the debug output.
   void dump() const;
+
+private:
+  /// Adds live-in registers from basic block @p MBB, taking associated
+  /// lane masks into consideration.
+  void addBlockLiveIns(const MachineBasicBlock &MBB);
 };
 
 inline raw_ostream &operator<<(raw_ostream &OS, const LivePhysRegs& LR) {
   LR.print(OS);
   return OS;
 }
 
 } // namespace llvm
 
 #endif

lib/CodeGen/LivePhysRegs.cpp

bool LivePhysRegs::available(const MachineRegisterInfo &MRI,
   for (MCRegAliasIterator R(Reg, TRI, false); R.isValid(); ++R) {
     if (LiveRegs.count(*R))
       return false;
   }
   return true;
 }
 
 /// Add live-in registers of basic block \p MBB to \p LiveRegs.
-static void addLiveIns(LivePhysRegs &LiveRegs, const MachineBasicBlock &MBB) {
-  for (const auto &LI : MBB.liveins())
-    LiveRegs.addReg(LI.PhysReg);
+void LivePhysRegs::addBlockLiveIns(const MachineBasicBlock &MBB) {
+  for (const auto &LI : MBB.liveins()) {
+    if (LI.LaneMask == ~0u) {
+      addReg(LI.PhysReg);
+      continue;
+    }
+    for (MCSubRegIndexIterator S(LI.PhysReg, TRI); S.isValid(); ++S)
+      if (LI.LaneMask & TRI->getSubRegIndexLaneMask(S.getSubRegIndex()))
+        addReg(S.getSubReg());
+  }
 }
 
 /// Add pristine registers to the given \p LiveRegs. This function removes
 /// actually saved callee save registers when \p InPrologueEpilogue is false.
 static void addPristines(LivePhysRegs &LiveRegs, const MachineFunction &MF,
                          const MachineFrameInfo &MFI,
                          const TargetRegisterInfo &TRI) {
   for (const MCPhysReg *CSR = TRI.getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
     LiveRegs.addReg(*CSR);
   for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
     LiveRegs.removeReg(Info.getReg());
 }
 
 void LivePhysRegs::addLiveOutsNoPristines(const MachineBasicBlock &MBB) {
   // To get the live-outs we simply merge the live-ins of all successors.
   for (const MachineBasicBlock *Succ : MBB.successors())
-    ::addLiveIns(*this, *Succ);
+    addBlockLiveIns(*Succ);
 }
 
 void LivePhysRegs::addLiveOuts(const MachineBasicBlock &MBB) {
   const MachineFunction &MF = *MBB.getParent();
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   if (MFI.isCalleeSavedInfoValid()) {
     if (MBB.isReturnBlock()) {
       // The return block has no successors whose live-ins we could merge
       // below. So instead we add the callee saved registers manually.
       for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I)
         addReg(*I);
     } else {
       addPristines(*this, MF, MFI, *TRI);
     }
   }
 
   addLiveOutsNoPristines(MBB);
 }
 
 void LivePhysRegs::addLiveIns(const MachineBasicBlock &MBB) {
   const MachineFunction &MF = *MBB.getParent();
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   if (MFI.isCalleeSavedInfoValid())
     addPristines(*this, MF, MFI, *TRI);
-  ::addLiveIns(*this, MBB);
+  addBlockLiveIns(MBB);
 }

test/CodeGen/Hexagon/livephysregs-lane-masks.mir

+# RUN: llc -march=hexagon -run-pass if-converter -verify-machineinstrs -o - %s | FileCheck %s
+
+# CHECK-LABEL: name: foo
+# CHECK: %p0 = C2_cmpeqi %r16, 0
+# Make sure there is no implicit use of r1.
+# CHECK: %r1 = L2_ploadruhf_io %p0, %r29, 6
+
+--- |
+  define void @foo() {
+    ret void
+  }
+...
+
+
+---
+name: foo
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: %r16
+    successors: %bb.1, %bb.2
+        %p0 = C2_cmpeqi %r16, 0
+        J2_jumpt %p0, %bb.2, implicit-def %pc
+
+  bb.1:
+    ; The lane mask %d0:0002 is equivalent to %r0. LivePhysRegs would ignore
+    ; it and treat it as the whole %d0, which is a pair %r1, %r0. The extra
+    ; %r1 would cause an (undefined) implicit use to be added during
+    ; if-conversion.
+    liveins: %d0:0x00000002, %d15:0x00000001, %r16
+    successors: %bb.2
+        %r1 = L2_loadruh_io %r29, 6
+        S2_storeri_io killed %r16, 0, %r1
+
+  bb.2:
+    liveins: %r0
+        %d8 = L2_loadrd_io %r29, 8
+        L4_return implicit-def %r29, implicit-def %r30, implicit-def %r31, implicit-def %pc, implicit %r30
+