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Differential D25202

LegalizeDAG: Implement PROMOTE for ISD::BITREVERSE
ClosedPublic

Authored by • tstellarAMD on Oct 3 2016, 11:23 AM.

Details

Reviewers
bogner
hfinkel
Commits
rGf80c1875a3b1: LegalizeDAG: Implement PROMOTE for ISD::BITREVERSE
rL284163: LegalizeDAG: Implement PROMOTE for ISD::BITREVERSE
Summary

This operation is promoted the same way was ISD::BSWAP. This will
prevent a regression in test/Target/AMDGOU/bitreverse.ll when i16
support is implemented.

Diff Detail

Repository
rL LLVM

Event Timeline

• tstellarAMD updated this revision to Diff 73308.Oct 3 2016, 11:23 AM
• tstellarAMD retitled this revision from to LegalizeDAG: Implement PROMOTE for ISD::BITREVERSE.
• tstellarAMD updated this object.
• tstellarAMD added a reviewer: bogner.
• tstellarAMD added a subscriber: llvm-commits.
Herald added a subscriber: wdng. · View Herald TranscriptOct 3 2016, 11:23 AM
hfinkel accepted this revision.Oct 3 2016, 11:30 AM
hfinkel added a reviewer: hfinkel.
hfinkel added a subscriber: hfinkel.

LGTM

This revision is now accepted and ready to land.Oct 3 2016, 11:30 AM
Closed by commit rL284163: LegalizeDAG: Implement PROMOTE for ISD::BITREVERSE (authored by tstellar). · Explain WhyOct 13 2016, 2:13 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
CodeGen/
SelectionDAG/
3 lines

Diff 74584

llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Show First 20 Lines • Show All 4,078 Lines • ▼ Show 20 Lines if (Node->getOpcode() == ISD::CTLZ ||
Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) { Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
// Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
DAG.getConstant(NVT.getSizeInBits() - DAG.getConstant(NVT.getSizeInBits() -
OVT.getSizeInBits(), dl, NVT)); OVT.getSizeInBits(), dl, NVT));
} }
Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
break; break;
case ISD::BITREVERSE:
case ISD::BSWAP: { case ISD::BSWAP: {
unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
Tmp1 = DAG.getNode( Tmp1 = DAG.getNode(
ISD::SRL, dl, NVT, Tmp1, ISD::SRL, dl, NVT, Tmp1,
DAG.getConstant(DiffBits, dl, DAG.getConstant(DiffBits, dl,
TLI.getShiftAmountTy(NVT, DAG.getDataLayout()))); TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
Results.push_back(Tmp1); Results.push_back(Tmp1);
break; break;
} }
case ISD::FP_TO_UINT: case ISD::FP_TO_UINT:
▲ Show 20 Lines • Show All 405 Lines • Show Last 20 Lines