[WebAssembly] Add just enough block-signature support to conform to the new rules.

[sunfish]

Summary

This reverts r281773 and makes LLVM emit block signatures as is now required.

[dschuff]

lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp

574

Not that you have any opinions about that, or anything :D

[sunfish]

lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp

574

Heh. Do you have any suggestions on what we can say instead? :-)

[dschuff]

lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp

486

This could be reverse(MF)?

574

I have no problem with opinionated and/or snarky comments as long as they are useful :) How about describing what the nature of the checks and/or what exactly we have to do? (Just so I'm clear in my own understanding, this is about the signatures for fallthrough-return blocks, right?) Speaking of, FixEndOfFunctionEnds is a little hard to parse, and in any case it fixes the block/loop and not the end, so maybe it could be called FixEndOfFunctionBlocks or FixFallthroughReturnSignatures or something like that?

lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.h

public:
   void printRegName(raw_ostream &OS, unsigned RegNo) const override;
   void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
                  const MCSubtargetInfo &STI) override;
 
   // Used by tblegen code.
   void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printWebAssemblyP2AlignOperand(const MCInst *MI, unsigned OpNo,
                                       raw_ostream &O);
+  void printWebAssemblySignatureOperand(const MCInst *MI, unsigned OpNo,
+                                        raw_ostream &O);
 
   // Autogenerated by tblgen.
   void printInstruction(const MCInst *MI, raw_ostream &O);
   static const char *getRegisterName(unsigned RegNo);
 };
 
 namespace WebAssembly {
 
 const char *TypeToString(MVT Ty);
 
 } // end namespace WebAssembly
 
 } // end namespace llvm
 
 #endif

lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp

WebAssemblyInstPrinter::printWebAssemblyP2AlignOperand(const MCInst *MI,
                                                        unsigned OpNo,
                                                        raw_ostream &O) {
   int64_t Imm = MI->getOperand(OpNo).getImm();
   if (Imm == WebAssembly::GetDefaultP2Align(MI->getOpcode()))
     return;
   O << ":p2align=" << Imm;
 }
 
+void
+WebAssemblyInstPrinter::printWebAssemblySignatureOperand(const MCInst *MI,
+                                                         unsigned OpNo,
+                                                         raw_ostream &O) {
+  int64_t Imm = MI->getOperand(OpNo).getImm();
+  switch (Imm) {
+  case WebAssembly::Void: break;
+  case WebAssembly::I32: O << "i32"; break;
+  case WebAssembly::I64: O << "i64"; break;
+  case WebAssembly::F32: O << "f32"; break;
+  case WebAssembly::F64: O << "f64"; break;
+  case WebAssembly::I8x16: O << "i8x16"; break;
+  case WebAssembly::I16x8: O << "i16x8"; break;
+  case WebAssembly::I32x4: O << "i32x4"; break;
+  case WebAssembly::I64x2: O << "i32x4"; break;
+  case WebAssembly::F32x4: O << "f32x4"; break;
+  case WebAssembly::F64x2: O << "f64x2"; break;
+  }
+}
+
 const char *llvm::WebAssembly::TypeToString(MVT Ty) {
   switch (Ty.SimpleTy) {
   case MVT::i32:
     return "i32";
   case MVT::i64:
     return "i64";
   case MVT::f32:
     return "f32";

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h

 enum OperandType {
   /// Basic block label in a branch construct.
   OPERAND_BASIC_BLOCK = MCOI::OPERAND_FIRST_TARGET,
   /// 32-bit floating-point immediates.
   OPERAND_FP32IMM,
   /// 64-bit floating-point immediates.
   OPERAND_FP64IMM,
   /// p2align immediate for load and store address alignment.
-  OPERAND_P2ALIGN
+  OPERAND_P2ALIGN,
+  /// signature immediate for block/loop.
+  OPERAND_SIGNATURE
 };
 
 /// WebAssembly-specific directive identifiers.
 enum Directive {
   // FIXME: This is not the real binary encoding.
   DotParam = UINT64_MAX - 0,   ///< .param
   DotResult = UINT64_MAX - 1,  ///< .result
   DotLocal = UINT64_MAX - 2,   ///< .local
   DotEndFunc = UINT64_MAX - 3, ///< .endfunc
-  DotIndIdx = UINT64_MAX - 4,  /// < .indidx
+  DotIndIdx = UINT64_MAX - 4,  ///< .indidx
 };
 
 } // end namespace WebAssembly
 
 namespace WebAssemblyII {
 enum {
   // For variadic instructions, this flag indicates whether an operand
   // in the variable_ops range is an immediate value.
inline unsigned GetDefaultP2Align(unsigned Opcode) {
   }
 }
 
 /// The operand number of the load or store address in load/store instructions.
 static const unsigned MemOpAddressOperandNo = 2;
 /// The operand number of the stored value in a store instruction.
 static const unsigned StoreValueOperandNo = 4;
 
+/// This is used to indicate block signatures.
+enum ExprType {
+  Void = 0,
+  I32  = 1,
+  I64  = 2,
+  F32  = 3,
+  F64  = 4,
+  I8x16 = 5,
+  I16x8 = 6,
+  I32x4 = 7,
+  I64x2 = 8,
+  F32x4 = 9,
+  F64x2 = 10
+};
+
 } // end namespace WebAssembly
 } // end namespace llvm
 
 #endif

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.h

public:
   /// .result
   virtual void emitResult(ArrayRef<MVT> Types) = 0;
   /// .local
   virtual void emitLocal(ArrayRef<MVT> Types) = 0;
   /// .endfunc
   virtual void emitEndFunc() = 0;
   /// .functype
   virtual void emitIndirectFunctionType(StringRef name,
-                                        SmallVectorImpl<MVT> &SignatureVTs,
-                                        size_t NumResults) {
+                                        SmallVectorImpl<MVT> &Params,
+                                        SmallVectorImpl<MVT> &Results) {
     llvm_unreachable("emitIndirectFunctionType not implemented");
   }
   /// .indidx
   virtual void emitIndIdx(const MCExpr *Value) = 0;
 };
 
 /// This part is for ascii assembly output
 class WebAssemblyTargetAsmStreamer final : public WebAssemblyTargetStreamer {
   formatted_raw_ostream &OS;
 
 public:
   WebAssemblyTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS);
 
   void emitParam(ArrayRef<MVT> Types) override;
   void emitResult(ArrayRef<MVT> Types) override;
   void emitLocal(ArrayRef<MVT> Types) override;
   void emitEndFunc() override;
   void emitIndirectFunctionType(StringRef name,
-                                SmallVectorImpl<MVT> &SignatureVTs,
-                                size_t NumResults) override;
+                                SmallVectorImpl<MVT> &Params,
+                                SmallVectorImpl<MVT> &Results) override;
   void emitIndIdx(const MCExpr *Value) override;
 };
 
 /// This part is for ELF object output
 class WebAssemblyTargetELFStreamer final : public WebAssemblyTargetStreamer {
 public:
   explicit WebAssemblyTargetELFStreamer(MCStreamer &S);
 

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.cpp

 void WebAssemblyTargetAsmStreamer::emitLocal(ArrayRef<MVT> Types) {
   OS << "\t.local  \t";
   PrintTypes(OS, Types);
 }
 
 void WebAssemblyTargetAsmStreamer::emitEndFunc() { OS << "\t.endfunc\n"; }
 
 void WebAssemblyTargetAsmStreamer::emitIndirectFunctionType(
-    StringRef name, SmallVectorImpl<MVT> &SignatureVTs, size_t NumResults) {
+    StringRef name, SmallVectorImpl<MVT> &Params, SmallVectorImpl<MVT> &Results) {
   OS << "\t.functype\t" << name;
-  if (NumResults == 0)
+  if (Results.empty())
     OS << ", void";
-  for (auto Ty : SignatureVTs) {
-    OS << ", " << WebAssembly::TypeToString(Ty);
+  else {
+    assert(Results.size() == 1);
+    OS << ", " << WebAssembly::TypeToString(Results.front());
   }
-  OS << "\n";
+  for (auto Ty : Params)
+    OS << ", " << WebAssembly::TypeToString(Ty);
+  OS << '\n';
 }
 
 void WebAssemblyTargetAsmStreamer::emitIndIdx(const MCExpr *Value) {
   OS << "\t.indidx  \t" << *Value << '\n';
 }
 
 // FIXME: What follows is not the real binary encoding.
 

lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

 WebAssemblyTargetStreamer *WebAssemblyAsmPrinter::getTargetStreamer() {
   MCTargetStreamer *TS = OutStreamer->getTargetStreamer();
   return static_cast<WebAssemblyTargetStreamer *>(TS);
 }
 
 //===----------------------------------------------------------------------===//
 // WebAssemblyAsmPrinter Implementation.
 //===----------------------------------------------------------------------===//
-static void ComputeLegalValueVTs(const Function &F, const TargetMachine &TM,
-                                 Type *Ty, SmallVectorImpl<MVT> &ValueVTs) {
-  const DataLayout &DL(F.getParent()->getDataLayout());
-  const WebAssemblyTargetLowering &TLI =
-      *TM.getSubtarget<WebAssemblySubtarget>(F).getTargetLowering();
-  SmallVector<EVT, 4> VTs;
-  ComputeValueVTs(TLI, DL, Ty, VTs);
-
-  for (EVT VT : VTs) {
-    unsigned NumRegs = TLI.getNumRegisters(F.getContext(), VT);
-    MVT RegisterVT = TLI.getRegisterType(F.getContext(), VT);
-    for (unsigned i = 0; i != NumRegs; ++i)
-      ValueVTs.push_back(RegisterVT);
-  }
-}
 
 void WebAssemblyAsmPrinter::EmitEndOfAsmFile(Module &M) {
   for (const auto &F : M) {
     // Emit function type info for all undefined functions
     if (F.isDeclarationForLinker() && !F.isIntrinsic()) {
-      SmallVector<MVT, 4> SignatureVTs;
-      ComputeLegalValueVTs(F, TM, F.getReturnType(), SignatureVTs);
-      size_t NumResults = SignatureVTs.size();
-      if (SignatureVTs.size() > 1) {
-        // WebAssembly currently can't lower returns of multiple values without
-        // demoting to sret (see WebAssemblyTargetLowering::CanLowerReturn). So
-        // replace multiple return values with a pointer parameter.
-        SignatureVTs.clear();
-        SignatureVTs.push_back(
-            MVT::getIntegerVT(M.getDataLayout().getPointerSizeInBits()));
-        NumResults = 0;
-      }
-
-      for (auto &Arg : F.args()) {
-        ComputeLegalValueVTs(F, TM, Arg.getType(), SignatureVTs);
-      }
-
-      getTargetStreamer()->emitIndirectFunctionType(F.getName(), SignatureVTs,
-                                                    NumResults);
+      SmallVector<MVT, 4> Results;
+      SmallVector<MVT, 4> Params;
+      ComputeSignatureVTs(F, TM, Params, Results);
+      getTargetStreamer()->emitIndirectFunctionType(F.getName(), Params,
+                                                    Results);
     }
   }
 }
 
 void WebAssemblyAsmPrinter::EmitConstantPool() {
   assert(MF->getConstantPool()->getConstants().empty() &&
          "WebAssembly disables constant pools");
 }

lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp

static bool IsChild(const MachineInstr &MI,
   if (!MO.isReg() || MO.isImplicit() || !MO.isDef())
     return false;
   unsigned Reg = MO.getReg();
   return TargetRegisterInfo::isVirtualRegister(Reg) &&
          MFI.isVRegStackified(Reg);
 }
 
 /// Insert a BLOCK marker for branches to MBB (if needed).
-static void PlaceBlockMarker(MachineBasicBlock &MBB, MachineFunction &MF,
-                             SmallVectorImpl<MachineBasicBlock *> &ScopeTops,
-                             const WebAssemblyInstrInfo &TII,
-                             const MachineLoopInfo &MLI,
-                             MachineDominatorTree &MDT,
-                             WebAssemblyFunctionInfo &MFI) {
+static void PlaceBlockMarker(
+    MachineBasicBlock &MBB, MachineFunction &MF,
+    DenseMap<const MachineInstr *, MachineInstr *> &BlockTops,
   // First compute the nearest common dominator of all forward non-fallthrough
   // predecessors so that we minimize the time that the BLOCK is on the stack,
   // which reduces overall stack height.
   MachineBasicBlock *Header = nullptr;
   bool IsBranchedTo = false;
   int MBBNumber = MBB.getNumber();
   for (MachineBasicBlock *Pred : MBB.predecessors())
     if (Pred->getNumber() < MBBNumber) {
while (InsertPos != Header->begin() &&
            IsChild(*std::prev(InsertPos), MFI) &&
            std::prev(InsertPos)->getOpcode() != WebAssembly::LOOP &&
            std::prev(InsertPos)->getOpcode() != WebAssembly::END_BLOCK &&
            std::prev(InsertPos)->getOpcode() != WebAssembly::END_LOOP)
       --InsertPos;
   }
 
   // Add the BLOCK.
-  BuildMI(*Header, InsertPos, DebugLoc(), TII.get(WebAssembly::BLOCK));
+  MachineInstr *Begin = BuildMI(*Header, InsertPos, DebugLoc(),
+                                TII.get(WebAssembly::BLOCK))
+      .addImm(WebAssembly::Void);
 
   // Mark the end of the block.
   InsertPos = MBB.begin();
   while (InsertPos != MBB.end() &&
          InsertPos->getOpcode() == WebAssembly::END_LOOP)
     ++InsertPos;
-  BuildMI(MBB, InsertPos, DebugLoc(), TII.get(WebAssembly::END_BLOCK));
+  MachineInstr *End = BuildMI(MBB, InsertPos, DebugLoc(),
+                              TII.get(WebAssembly::END_BLOCK));
+  BlockTops[End] = Begin;
 
   // Track the farthest-spanning scope that ends at this point.
   int Number = MBB.getNumber();
   if (!ScopeTops[Number] ||
       ScopeTops[Number]->getNumber() > Header->getNumber())
     ScopeTops[Number] = Header;
 }
 
 /// Insert a LOOP marker for a loop starting at MBB (if it's a loop header).
 static void PlaceLoopMarker(
     MachineBasicBlock &MBB, MachineFunction &MF,
     SmallVectorImpl<MachineBasicBlock *> &ScopeTops,
-    DenseMap<const MachineInstr *, const MachineBasicBlock *> &LoopTops,
+    DenseMap<const MachineInstr *, MachineInstr *> &LoopTops,
     const WebAssemblyInstrInfo &TII, const MachineLoopInfo &MLI) {
   MachineLoop *Loop = MLI.getLoopFor(&MBB);
   if (!Loop || Loop->getHeader() != &MBB)
     return;
 
   // The operand of a LOOP is the first block after the loop. If the loop is the
   // bottom of the function, insert a dummy block at the end.
   MachineBasicBlock *Bottom = LoopBottom(Loop);
   auto Iter = std::next(MachineFunction::iterator(Bottom));
   if (Iter == MF.end()) {
     MachineBasicBlock *Label = MF.CreateMachineBasicBlock();
     // Give it a fake predecessor so that AsmPrinter prints its label.
     Label->addSuccessor(Label);
     MF.push_back(Label);
     Iter = std::next(MachineFunction::iterator(Bottom));
   }
   MachineBasicBlock *AfterLoop = &*Iter;
 
   // Mark the beginning of the loop (after the end of any existing loop that
   // ends here).
   auto InsertPos = MBB.begin();
   while (InsertPos != MBB.end() &&
          InsertPos->getOpcode() == WebAssembly::END_LOOP)
     ++InsertPos;
-  BuildMI(MBB, InsertPos, DebugLoc(), TII.get(WebAssembly::LOOP));
+  MachineInstr *Begin = BuildMI(MBB, InsertPos, DebugLoc(),
+                                TII.get(WebAssembly::LOOP))
+      .addImm(WebAssembly::Void);
 
   // Mark the end of the loop.
   MachineInstr *End = BuildMI(*AfterLoop, AfterLoop->begin(), DebugLoc(),
                               TII.get(WebAssembly::END_LOOP));
-  LoopTops[End] = &MBB;
+  LoopTops[End] = Begin;
 
   assert((!ScopeTops[AfterLoop->getNumber()] ||
           ScopeTops[AfterLoop->getNumber()]->getNumber() < MBB.getNumber()) &&
          "With block sorting the outermost loop for a block should be first.");
   if (!ScopeTops[AfterLoop->getNumber()])
     ScopeTops[AfterLoop->getNumber()] = &MBB;
 }
 
 static unsigned
 GetDepth(const SmallVectorImpl<const MachineBasicBlock *> &Stack,
          const MachineBasicBlock *MBB) {
   unsigned Depth = 0;
   for (auto X : reverse(Stack)) {
     if (X == MBB)
       break;
     ++Depth;
   }
   assert(Depth < Stack.size() && "Branch destination should be in scope");
   return Depth;
 }
 
+static void FixEndOfFunctionEnds(
+    MachineFunction &MF,
+    const WebAssemblyFunctionInfo &MFI,
+    DenseMap<const MachineInstr *, MachineInstr *> &BlockTops,
+    DenseMap<const MachineInstr *, MachineInstr *> &LoopTops) {
+  assert(MFI.getResults().size() <= 1);
+
+  if (MFI.getResults().empty())
+    return;
+
+  WebAssembly::ExprType retType;
+  switch (MFI.getResults().front().SimpleTy) {
+  case MVT::i32: retType = WebAssembly::I32; break;
+  case MVT::i64: retType = WebAssembly::I64; break;
+  case MVT::f32: retType = WebAssembly::F32; break;
+  case MVT::f64: retType = WebAssembly::F64; break;
+  case MVT::v16i8: retType = WebAssembly::I8x16; break;
+  case MVT::v8i16: retType = WebAssembly::I16x8; break;
+  case MVT::v4i32: retType = WebAssembly::I32x4; break;
+  case MVT::v2i64: retType = WebAssembly::I64x2; break;
+  case MVT::v4f32: retType = WebAssembly::F32x4; break;
+  case MVT::v2f64: retType = WebAssembly::F64x2; break;
+  default: llvm_unreachable("unexpected return type");
+  }
+
+  for (MachineFunction::reverse_iterator MBBI = MF.rbegin();
+       MBBI != MF.rend(); ++MBBI) {
+    for (MachineBasicBlock::reverse_iterator MII = MBBI->rbegin();
+         MII != MBBI->rend(); ++MII) {
+      MachineInstr &MI = *MII;
+      if (MI.isPosition() || MI.isDebugValue())
+        continue;
+      if (MI.getOpcode() == WebAssembly::END_BLOCK) {
+        BlockTops[&MI]->getOperand(0).setImm(int32_t(retType));
+        continue;
+      }
+      if (MI.getOpcode() == WebAssembly::END_LOOP) {
+        LoopTops[&MI]->getOperand(0).setImm(int32_t(retType));
+        continue;
+      }
+      // Something other than an `end`. We're done.
+      return;
+    }
+  }
+}
+
 /// Insert LOOP and BLOCK markers at appropriate places.
 static void PlaceMarkers(MachineFunction &MF, const MachineLoopInfo &MLI,
                          const WebAssemblyInstrInfo &TII,
                          MachineDominatorTree &MDT,
                          WebAssemblyFunctionInfo &MFI) {
   // For each block whose label represents the end of a scope, record the block
   // which holds the beginning of the scope. This will allow us to quickly skip
   // over scoped regions when walking blocks. We allocate one more than the
   // number of blocks in the function to accommodate for the possible fake block
   // we may insert at the end.
   SmallVector<MachineBasicBlock *, 8> ScopeTops(MF.getNumBlockIDs() + 1);
 
-  // For eacn LOOP_END, the corresponding LOOP.
-  DenseMap<const MachineInstr *, const MachineBasicBlock *> LoopTops;
+  // For each END_LOOP, the corresponding LOOP.
+  DenseMap<const MachineInstr *, MachineInstr *> LoopTops;
+
+  // For each END_BLOCK, the corresponding BLOCK.
+  DenseMap<const MachineInstr *, MachineInstr *> BlockTops;
 
   for (auto &MBB : MF) {
     // Place the LOOP for MBB if MBB is the header of a loop.
     PlaceLoopMarker(MBB, MF, ScopeTops, LoopTops, TII, MLI);
 
     // Place the BLOCK for MBB if MBB is branched to from above.
-    PlaceBlockMarker(MBB, MF, ScopeTops, TII, MLI, MDT, MFI);
+    PlaceBlockMarker(MBB, MF, ScopeTops, BlockTops, TII, MLI, MDT, MFI);
   }
 
   // Now rewrite references to basic blocks to be depth immediates.
   SmallVector<const MachineBasicBlock *, 8> Stack;
   for (auto &MBB : reverse(MF)) {
     for (auto &MI : reverse(MBB)) {
       switch (MI.getOpcode()) {
       case WebAssembly::BLOCK:
         assert(ScopeTops[Stack.back()->getNumber()] == &MBB &&
                "Block should be balanced");
         Stack.pop_back();
         break;
       case WebAssembly::LOOP:
         assert(Stack.back() == &MBB && "Loop top should be balanced");
         Stack.pop_back();
         Stack.pop_back();
         break;
       case WebAssembly::END_BLOCK:
         Stack.push_back(&MBB);
         break;
       case WebAssembly::END_LOOP:
         Stack.push_back(&MBB);
-        Stack.push_back(LoopTops[&MI]);
+        Stack.push_back(LoopTops[&MI]->getParent());
         break;
       default:
         if (MI.isTerminator()) {
           // Rewrite MBB operands to be depth immediates.
           SmallVector<MachineOperand, 4> Ops(MI.operands());
           while (MI.getNumOperands() > 0)
             MI.RemoveOperand(MI.getNumOperands() - 1);
           for (auto MO : Ops) {
             if (MO.isMBB())
               MO = MachineOperand::CreateImm(GetDepth(Stack, MO.getMBB()));
             MI.addOperand(MF, MO);
           }
         }
         break;
       }
     }
   }
   assert(Stack.empty() && "Control flow should be balanced");
+
+  // Some browsers have choosen to impose additional and non-essential
+  // type-checking errors. Do additional work to satisfy them.
+  FixEndOfFunctionEnds(MF, MFI, BlockTops, LoopTops);
 }
 
 bool WebAssemblyCFGStackify::runOnMachineFunction(MachineFunction &MF) {
   DEBUG(dbgs() << "********** CFG Stackifying **********\n"
                   "********** Function: "
                << MF.getName() << '\n');
 
   const auto &MLI = getAnalysis<MachineLoopInfo>();

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

SDValue WebAssemblyTargetLowering::LowerReturn(
 
   return Chain;
 }
 
 SDValue WebAssemblyTargetLowering::LowerFormalArguments(
     SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
-  MachineFunction &MF = DAG.getMachineFunction();
-  auto *MFI = MF.getInfo<WebAssemblyFunctionInfo>();
-
   if (!CallingConvSupported(CallConv))
     fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
 
+  MachineFunction &MF = DAG.getMachineFunction();
+  auto *MFI = MF.getInfo<WebAssemblyFunctionInfo>();
+
   // Set up the incoming ARGUMENTS value, which serves to represent the liveness
   // of the incoming values before they're represented by virtual registers.
   MF.getRegInfo().addLiveIn(WebAssembly::ARGUMENTS);
 
   for (const ISD::InputArg &In : Ins) {
     if (In.Flags.isInAlloca())
       fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
     if (In.Flags.isNest())
if (IsVarArg) {
     MFI->setVarargBufferVreg(VarargVreg);
     Chain = DAG.getCopyToReg(
         Chain, DL, VarargVreg,
         DAG.getNode(WebAssemblyISD::ARGUMENT, DL, PtrVT,
                     DAG.getTargetConstant(Ins.size(), DL, MVT::i32)));
     MFI->addParam(PtrVT);
   }
 
+  // Record the number and types of results.
+  SmallVector<MVT, 4> Params;
+  SmallVector<MVT, 4> Results;
+  ComputeSignatureVTs(*MF.getFunction(), DAG.getTarget(), Params, Results);
+  for (MVT VT : Results)
+    MFI->addResult(VT);
+
   return Chain;
 }
 
 //===----------------------------------------------------------------------===//
 //  Custom lowering hooks.
 //===----------------------------------------------------------------------===//
 
 SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op,

lib/Target/WebAssembly/WebAssemblyInstrControl.td

def BR_TABLE_I64 : I<(outs), (ins I64:$index, variable_ops),
   let TSFlags{1} = 1;
 }
 } // isTerminator = 1, hasCtrlDep = 1, isBarrier = 1
 
 // Placemarkers to indicate the start or end of a block or loop scope. These
 // use/clobber EXPR_STACK to prevent them from being moved into the middle of
 // an expression tree.
 let Uses = [EXPR_STACK], Defs = [EXPR_STACK] in {
-def BLOCK     : I<(outs), (ins), [], "block">;
-def LOOP      : I<(outs), (ins), [], "loop">;
+def BLOCK     : I<(outs), (ins Signature:$sig), [], "block   \t$sig">;
+def LOOP      : I<(outs), (ins Signature:$sig), [], "loop    \t$sig">;
 def END_BLOCK : I<(outs), (ins), [], "end_block">;
 def END_LOOP  : I<(outs), (ins), [], "end_loop">;
 } // Uses = [EXPR_STACK], Defs = [EXPR_STACK]
 
 multiclass RETURN<WebAssemblyRegClass vt> {
   def RETURN_#vt : I<(outs), (ins vt:$val), [(WebAssemblyreturn vt:$val)],
                      "return  \t$val">;
   // Equivalent to RETURN_#vt, for use at the end of a function when wasm

lib/Target/WebAssembly/WebAssemblyInstrInfo.td

 def f64imm_op : Operand<f64>;
 
 let OperandType = "OPERAND_P2ALIGN" in {
 def P2Align : Operand<i32> {
   let PrintMethod = "printWebAssemblyP2AlignOperand";
 }
 } // OperandType = "OPERAND_P2ALIGN"
 
+let OperandType = "OPERAND_SIGNATURE" in {
+def Signature : Operand<i32> {
+  let PrintMethod = "printWebAssemblySignatureOperand";
+}
+} // OperandType = "OPERAND_SIGNATURE"
+
 } // OperandNamespace = "WebAssembly"
 
 //===----------------------------------------------------------------------===//
 // WebAssembly Instruction Format Definitions.
 //===----------------------------------------------------------------------===//
 
 include "WebAssemblyInstrFormats.td"
 

lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h

 namespace llvm {
 
 /// This class is derived from MachineFunctionInfo and contains private
 /// WebAssembly-specific information for each MachineFunction.
 class WebAssemblyFunctionInfo final : public MachineFunctionInfo {
   MachineFunction &MF;
 
   std::vector<MVT> Params;
+  std::vector<MVT> Results;
 
   /// A mapping from CodeGen vreg index to WebAssembly register number.
   std::vector<unsigned> WARegs;
 
   /// A mapping from CodeGen vreg index to a boolean value indicating whether
   /// the given register is considered to be "stackified", meaning it has been
   /// determined or made to meet the stack requirements:
   ///   - single use (per path)
   ///   - single def (per path)
   ///   - defined and used in LIFO order with other stack registers
   BitVector VRegStackified;
 
   // A virtual register holding the pointer to the vararg buffer for vararg
   // functions. It is created and set in TLI::LowerFormalArguments and read by
   // TLI::LowerVASTART
   unsigned VarargVreg = -1U;
 
  public:
   explicit WebAssemblyFunctionInfo(MachineFunction &MF) : MF(MF) {}
   ~WebAssemblyFunctionInfo() override;
 
   void addParam(MVT VT) { Params.push_back(VT); }
   const std::vector<MVT> &getParams() const { return Params; }
 
+  void addResult(MVT VT) { Results.push_back(VT); }
+  const std::vector<MVT> &getResults() const { return Results; }
+
   unsigned getVarargBufferVreg() const {
     assert(VarargVreg != -1U && "Vararg vreg hasn't been set");
     return VarargVreg;
   }
   void setVarargBufferVreg(unsigned Reg) { VarargVreg = Reg; }
 
   static const unsigned UnusedReg = -1u;
 
public:
 
   // For a given stackified WAReg, return the id number to print with push/pop.
   static unsigned getWARegStackId(unsigned Reg) {
     assert(Reg & INT32_MIN);
     return Reg & INT32_MAX;
   }
 };
 
+void ComputeLegalValueVTs(const Function &F, const TargetMachine &TM,
+                          Type *Ty, SmallVectorImpl<MVT> &ValueVTs);
+
+void ComputeSignatureVTs(const Function &F, const TargetMachine &TM,
+                         SmallVectorImpl<MVT> &Params,
+                         SmallVectorImpl<MVT> &Results);
+
 } // end namespace llvm
 
 #endif

lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp

 //=- WebAssemblyMachineFunctionInfo.cpp - WebAssembly Machine Function Info -=//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief This file implements WebAssembly-specific per-machine-function
 /// information.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "WebAssemblyMachineFunctionInfo.h"
+#include "WebAssemblyISelLowering.h"
+#include "WebAssemblySubtarget.h"
+#include "llvm/CodeGen/Analysis.h"
 using namespace llvm;
 
 WebAssemblyFunctionInfo::~WebAssemblyFunctionInfo() {}
 
 void WebAssemblyFunctionInfo::initWARegs() {
   assert(WARegs.empty());
   unsigned Reg = UnusedReg;
   WARegs.resize(MF.getRegInfo().getNumVirtRegs(), Reg);
 }
+
+void llvm::ComputeLegalValueVTs(const Function &F, const TargetMachine &TM,
+                                Type *Ty, SmallVectorImpl<MVT> &ValueVTs) {
+  const DataLayout &DL(F.getParent()->getDataLayout());
+  const WebAssemblyTargetLowering &TLI =
+      *TM.getSubtarget<WebAssemblySubtarget>(F).getTargetLowering();
+  SmallVector<EVT, 4> VTs;
+  ComputeValueVTs(TLI, DL, Ty, VTs);
+
+  for (EVT VT : VTs) {
+    unsigned NumRegs = TLI.getNumRegisters(F.getContext(), VT);
+    MVT RegisterVT = TLI.getRegisterType(F.getContext(), VT);
+    for (unsigned i = 0; i != NumRegs; ++i)
+      ValueVTs.push_back(RegisterVT);
+  }
+}
+
+void llvm::ComputeSignatureVTs(const Function &F, const TargetMachine &TM,
+                               SmallVectorImpl<MVT> &Params,
+                               SmallVectorImpl<MVT> &Results) {
+  ComputeLegalValueVTs(F, TM, F.getReturnType(), Results);
+
+  if (Results.size() > 1) {
+    // WebAssembly currently can't lower returns of multiple values without
+    // demoting to sret (see WebAssemblyTargetLowering::CanLowerReturn). So
+    // replace multiple return values with a pointer parameter.
+    Results.clear();
+    Params.push_back(
+        MVT::getIntegerVT(TM.createDataLayout().getPointerSizeInBits()));
+  }
+
+  for (auto &Arg : F.args())
+    ComputeLegalValueVTs(F, TM, Arg.getType(), Params);
+}

test/CodeGen/WebAssembly/cfg-stackify.ll

back:
   call void @something()
   br label %header
 }
 
 ; Test that a simple loop is handled as expected.
 
 ; CHECK-LABEL: test2:
 ; CHECK-NOT: local
-; CHECK: block{{$}}
+; CHECK: block   {{$}}
 ; CHECK: br_if 0, {{[^,]+}}{{$}}
 ; CHECK: .LBB2_{{[0-9]+}}:
 ; CHECK: loop
 ; CHECK: br_if 0, $pop{{[0-9]+}}{{$}}
 ; CHECK: .LBB2_{{[0-9]+}}:
 ; CHECK: end_loop
 ; CHECK: end_block
 ; CHECK: return{{$}}
 ; OPT-LABEL: test2:
 ; OPT-NOT: local
-; OPT: block{{$}}
+; OPT: block   {{$}}
 ; OPT: br_if 0, {{[^,]+}}{{$}}
 ; OPT: .LBB2_{{[0-9]+}}:
 ; OPT: loop
 ; OPT: br_if 0, $pop{{[0-9]+}}{{$}}
 ; OPT: .LBB2_{{[0-9]+}}:
 ; OPT: end_loop
 ; OPT: end_block
 ; OPT: return{{$}}

 for.end.loopexit:
   br label %for.end
 
 for.end:
   ret void
 }
 
 ; CHECK-LABEL: doublediamond:
-; CHECK: block{{$}}
-; CHECK-NEXT: block{{$}}
+; CHECK: block   {{$}}
+; CHECK-NEXT: block   {{$}}
 ; CHECK: br_if 0, ${{[^,]+}}{{$}}
 ; CHECK: br 1{{$}}
 ; CHECK: .LBB3_2:
 ; CHECK-NEXT: end_block{{$}}
-; CHECK: block{{$}}
+; CHECK: block   {{$}}
 ; CHECK: br_if 0, ${{[^,]+}}{{$}}
 ; CHECK: br 1{{$}}
 ; CHECK: .LBB3_4:
 ; CHECK-NEXT: end_block{{$}}
 ; CHECK: .LBB3_5:
 ; CHECK-NEXT: end_block{{$}}
 ; CHECK: i32.const $push{{[0-9]+}}=, 0{{$}}
 ; CHECK-NEXT: return $pop{{[0-9]+}}{{$}}
 ; OPT-LABEL: doublediamond:
-; OPT:      block{{$}}
-; OPT-NEXT: block{{$}}
-; OPT-NEXT: block{{$}}
+; OPT:      block   {{$}}
+; OPT-NEXT: block   {{$}}
+; OPT-NEXT: block   {{$}}
 ; OPT:      br_if 0, ${{[^,]+}}{{$}}
 ; OPT:      br_if 1, ${{[^,]+}}{{$}}
 ; OPT:      br 2{{$}}
 ; OPT-NEXT: .LBB3_3:
 ; OPT-NEXT: end_block
 ; OPT:      br 1{{$}}
 ; OPT-NEXT: .LBB3_4:
 ; OPT:      .LBB3_5:
ff:
   store volatile i32 4, i32* %p
   br label %exit
 exit:
   store volatile i32 5, i32* %p
   ret i32 0
 }
 
 ; CHECK-LABEL: triangle:
-; CHECK: block{{$}}
+; CHECK: block   {{$}}
 ; CHECK: br_if 0, $1{{$}}
 ; CHECK: .LBB4_2:
 ; CHECK: return
 ; OPT-LABEL: triangle:
-; OPT: block{{$}}
+; OPT: block   {{$}}
 ; OPT: br_if 0, $1{{$}}
 ; OPT: .LBB4_2:
 ; OPT: return
 define i32 @triangle(i32* %p, i32 %a) {
 entry:
   %c = icmp eq i32 %a, 0
   store volatile i32 0, i32* %p
   br i1 %c, label %true, label %exit
 true:
   store volatile i32 1, i32* %p
   br label %exit
 exit:
   store volatile i32 2, i32* %p
   ret i32 0
 }
 
 ; CHECK-LABEL: diamond:
-; CHECK: block{{$}}
-; CHECK: block{{$}}
+; CHECK: block   {{$}}
+; CHECK: block   {{$}}
 ; CHECK: br_if 0, $1{{$}}
 ; CHECK: br 1{{$}}
 ; CHECK: .LBB5_2:
 ; CHECK: .LBB5_3:
 ; CHECK: i32.const $push{{[0-9]+}}=, 0{{$}}
 ; CHECK-NEXT: return $pop{{[0-9]+}}{{$}}
 ; OPT-LABEL: diamond:
-; OPT: block{{$}}
-; OPT: block{{$}}
+; OPT: block   {{$}}
+; OPT: block   {{$}}
 ; OPT: br_if 0, {{[^,]+}}{{$}}
 ; OPT: br 1{{$}}
 ; OPT: .LBB5_2:
 ; OPT: .LBB5_3:
 ; OPT: i32.const $push{{[0-9]+}}=, 0{{$}}
 ; OPT-NEXT: return $pop{{[0-9]+}}{{$}}
 define i32 @diamond(i32* %p, i32 %a) {
 entry:

 entry:
   store volatile i32 0, i32* %p
   ret i32 0
 }
 
 ; CHECK-LABEL: minimal_loop:
 ; CHECK-NOT: br
 ; CHECK: .LBB7_1:
+; CHECK: loop i32
 ; CHECK: i32.store $drop=, 0($0), $pop{{[0-9]+}}{{$}}
 ; CHECK: br 0{{$}}
 ; CHECK: .LBB7_2:
 ; OPT-LABEL: minimal_loop:
 ; OPT-NOT: br
 ; OPT: .LBB7_1:
+; OPT: loop i32
 ; OPT: i32.store $drop=, 0($0), $pop{{[0-9]+}}{{$}}
 ; OPT: br 0{{$}}
 ; OPT: .LBB7_2:
-define void @minimal_loop(i32* %p) {
+define i32 @minimal_loop(i32* %p) {
 entry:
   store volatile i32 0, i32* %p
   br label %loop
 loop:
   store volatile i32 1, i32* %p
   br label %loop
 }
 
 ; CHECK-LABEL: simple_loop:
 ; CHECK-NOT: br
 ; CHECK: .LBB8_1:
-; CHECK: loop{{$}}
+; CHECK: loop    {{$}}
 ; CHECK: br_if 0, $pop{{[0-9]+}}{{$}}
 ; CHECK-NEXT: end_loop{{$}}
 ; CHECK: i32.const $push{{[0-9]+}}=, 0{{$}}
 ; CHECK-NEXT: return $pop{{[0-9]+}}{{$}}
 ; OPT-LABEL: simple_loop:
 ; OPT-NOT: br
 ; OPT: .LBB8_1:
-; OPT: loop{{$}}
+; OPT: loop    {{$}}
 ; OPT: br_if 0, {{[^,]+}}{{$}}
 ; OPT-NEXT: end_loop{{$}}
 ; OPT: i32.const $push{{[0-9]+}}=, 0{{$}}
 ; OPT-NEXT: return $pop{{[0-9]+}}{{$}}
 define i32 @simple_loop(i32* %p, i32 %a) {
 entry:
   %c = icmp eq i32 %a, 0
   store volatile i32 0, i32* %p
   br label %loop
 loop:
   store volatile i32 1, i32* %p
   br i1 %c, label %loop, label %exit
 exit:
   store volatile i32 2, i32* %p
   ret i32 0
 }
 
 ; CHECK-LABEL: doubletriangle:
-; CHECK: block{{$}}
+; CHECK: block   {{$}}
 ; CHECK: br_if 0, $0{{$}}
-; CHECK: block{{$}}
+; CHECK: block   {{$}}
 ; CHECK: br_if 0, $1{{$}}
 ; CHECK: .LBB9_3:
 ; CHECK: .LBB9_4:
 ; CHECK: return
 ; OPT-LABEL: doubletriangle:
-; OPT: block{{$}}
+; OPT: block   {{$}}
 ; OPT: br_if 0, $0{{$}}
-; OPT: block{{$}}
+; OPT: block   {{$}}
 ; OPT: br_if 0, $1{{$}}
 ; OPT: .LBB9_3:
 ; OPT: .LBB9_4:
 ; OPT: return
 define i32 @doubletriangle(i32 %a, i32 %b, i32* %p) {
 entry:
   %c = icmp eq i32 %a, 0
   %d = icmp eq i32 %b, 0
tf:
   store volatile i32 4, i32* %p
   br label %exit
 exit:
   store volatile i32 5, i32* %p
   ret i32 0
 }
 
 ; CHECK-LABEL: ifelse_earlyexits:
-; CHECK: block{{$}}
-; CHECK: block{{$}}
+; CHECK: block   {{$}}
+; CHECK: block   {{$}}
 ; CHECK: br_if 0, $0{{$}}
 ; CHECK: br 1{{$}}
 ; CHECK: .LBB10_2:
 ; CHECK: br_if 0, $1{{$}}
 ; CHECK: .LBB10_4:
 ; CHECK: i32.const $push{{[0-9]+}}=, 0{{$}}
 ; CHECK-NEXT: return $pop{{[0-9]+}}{{$}}
 ; OPT-LABEL: ifelse_earlyexits:
-; OPT: block{{$}}
-; OPT: block{{$}}
+; OPT: block   {{$}}
+; OPT: block   {{$}}
 ; OPT: br_if 0, {{[^,]+}}{{$}}
 ; OPT: br_if 1, $1{{$}}
 ; OPT: br 1{{$}}
 ; OPT: .LBB10_3:
 ; OPT: .LBB10_4:
 ; OPT: i32.const $push{{[0-9]+}}=, 0{{$}}
 ; OPT-NEXT: return $pop{{[0-9]+}}{{$}}
 define i32 @ifelse_earlyexits(i32 %a, i32 %b, i32* %p) {
ft:
   br label %exit
 exit:
   store volatile i32 4, i32* %p
   ret i32 0
 }
 
 ; CHECK-LABEL: doublediamond_in_a_loop:
 ; CHECK: .LBB11_1:
-; CHECK: loop{{$}}
-; CHECK: block{{$}}
+; CHECK: loop i32{{$}}
+; CHECK: block   {{$}}
 ; CHECK: br_if           0, $0{{$}}
 ; CHECK: br              1{{$}}
 ; CHECK: .LBB11_3:
 ; CHECK: end_block{{$}}
-; CHECK: block{{$}}
+; CHECK: block   {{$}}
 ; CHECK: br_if           0, $1{{$}}
 ; CHECK: br              1{{$}}
 ; CHECK: .LBB11_5:
 ; CHECK: br              0{{$}}
 ; CHECK: .LBB11_6:
 ; CHECK-NEXT: end_loop{{$}}
 ; OPT-LABEL: doublediamond_in_a_loop:
 ; OPT:      .LBB11_1:
-; OPT:      loop{{$}}
-; OPT:      block{{$}}
+; OPT:      loop i32{{$}}
+; OPT:      block   {{$}}
 ; OPT:      br_if           0, {{[^,]+}}{{$}}
-; OPT:      block{{$}}
+; OPT:      block   {{$}}
 ; OPT:      br_if           0, {{[^,]+}}{{$}}
 ; OPT:      br              2{{$}}
 ; OPT-NEXT: .LBB11_4:
 ; OPT-NEXT: end_block{{$}}
 ; OPT:      br              1{{$}}
 ; OPT:      .LBB11_5:
 ; OPT-NEXT: end_block{{$}}
 ; OPT:      br              0{{$}}
 ; OPT:      .LBB11_6:
 ; OPT-NEXT: end_loop{{$}}
-define void @doublediamond_in_a_loop(i32 %a, i32 %b, i32* %p) {
+define i32 @doublediamond_in_a_loop(i32 %a, i32 %b, i32* %p) {
 entry:
   br label %header
 header:
   %c = icmp eq i32 %a, 0
   %d = icmp eq i32 %b, 0
   store volatile i32 0, i32* %p
   br i1 %c, label %true, label %false
 true:
if.end:
   call void @bar()
   br label %outer
 }
 
 ; Test switch lowering and block placement.
 
 ; CHECK-LABEL: test4:
 ; CHECK-NEXT: .param       i32{{$}}
-; CHECK:      block{{$}}
-; CHECK-NEXT: block{{$}}
+; CHECK:      block   {{$}}
+; CHECK-NEXT: block   {{$}}
 ; CHECK:      br_if       0, $pop{{[0-9]+}}{{$}}
 ; CHECK:      br_if       1, $pop{{[0-9]+}}{{$}}
 ; CHECK:      br          1{{$}}
 ; CHECK-NEXT: .LBB13_3:
 ; CHECK-NEXT: end_block{{$}}
-; CHECK-NEXT: block{{$}}
+; CHECK-NEXT: block   {{$}}
 ; CHECK:      br_if 0, $pop{{[0-9]+}}{{$}}
 ; CHECK:      br_if 1, $pop{{[0-9]+}}{{$}}
 ; CHECK-NEXT: .LBB13_5:
 ; CHECK-NEXT: end_block{{$}}
 ; CHECK-NEXT: return{{$}}
 ; CHECK-NEXT: .LBB13_6:
 ; CHECK-NEXT: end_block{{$}}
 ; CHECK-NEXT: return{{$}}
 ; OPT-LABEL: test4:
 ; OPT-NEXT: .param       i32{{$}}
-; OPT:      block{{$}}
-; OPT-NEXT: block{{$}}
+; OPT:      block   {{$}}
+; OPT-NEXT: block   {{$}}
 ; OPT:      br_if       0, $pop{{[0-9]+}}{{$}}
 ; OPT:      br_if       1, $pop{{[0-9]+}}{{$}}
 ; OPT:      br          1{{$}}
 ; OPT-NEXT: .LBB13_3:
 ; OPT-NEXT: end_block{{$}}
-; OPT-NEXT: block{{$}}
+; OPT-NEXT: block   {{$}}
 ; OPT:      br_if       0, $pop{{[0-9]+}}{{$}}
 ; OPT:      br_if       1, $pop{{[0-9]+}}{{$}}
 ; OPT-NEXT: .LBB13_5:
 ; OPT-NEXT: end_block{{$}}
 ; OPT-NEXT: return{{$}}
 ; OPT-NEXT: .LBB13_6:
 ; OPT-NEXT: end_block{{$}}
 ; OPT-NEXT: return{{$}}
default:
   ret void
 }
 
 ; Test a case where the BLOCK needs to be placed before the LOOP in the
 ; same basic block.
 
 ; CHECK-LABEL: test5:
 ; CHECK:       .LBB14_1:
-; CHECK-NEXT:  block{{$}}
-; CHECK-NEXT:  loop{{$}}
+; CHECK-NEXT:  block   {{$}}
+; CHECK-NEXT:  loop    {{$}}
 ; CHECK:       br_if 2, {{[^,]+}}{{$}}
 ; CHECK:       br_if 0, {{[^,]+}}{{$}}
 ; CHECK-NEXT:  end_loop{{$}}
 ; CHECK:       return{{$}}
 ; CHECK-NEXT:  .LBB14_4:
 ; CHECK:       return{{$}}
 ; OPT-LABEL: test5:
 ; OPT:       .LBB14_1:
-; OPT-NEXT:  block{{$}}
-; OPT-NEXT:  loop{{$}}
+; OPT-NEXT:  block   {{$}}
+; OPT-NEXT:  loop    {{$}}
 ; OPT:       br_if 2, {{[^,]+}}{{$}}
 ; OPT:       br_if 0, {{[^,]+}}{{$}}
 ; OPT-NEXT:  end_loop{{$}}
 ; OPT:       return{{$}}
 ; OPT-NEXT:  .LBB14_4:
 ; OPT:       return{{$}}
 define void @test5(i1 %p, i1 %q) {
 entry:

 }
 
 ; Test an interesting case of a loop with multiple exits, which
 ; aren't to layout successors of the loop, and one of which is to a successors
 ; which has another predecessor.
 
 ; CHECK-LABEL: test6:
 ; CHECK:       .LBB15_1:
-; CHECK-NEXT:  block{{$}}
-; CHECK-NEXT:  block{{$}}
-; CHECK-NEXT:  loop{{$}}
+; CHECK-NEXT:  block   {{$}}
+; CHECK-NEXT:  block   {{$}}
+; CHECK-NEXT:  loop    {{$}}
 ; CHECK-NOT:   block
 ; CHECK:       br_if 3, {{[^,]+}}{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       br_if 2, {{[^,]+}}{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       br_if 0, {{[^,]+}}{{$}}
 ; CHECK-NEXT:  end_loop{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       return{{$}}
 ; CHECK-NEXT:  .LBB15_5:
 ; CHECK-NEXT:  end_block{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       .LBB15_6:
 ; CHECK-NEXT:  end_block{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       return{{$}}
 ; OPT-LABEL: test6:
 ; OPT:       .LBB15_1:
-; OPT-NEXT:  block{{$}}
-; OPT-NEXT:  block{{$}}
-; OPT-NEXT:  loop{{$}}
+; OPT-NEXT:  block   {{$}}
+; OPT-NEXT:  block   {{$}}
+; OPT-NEXT:  loop    {{$}}
 ; OPT-NOT:   block
 ; OPT:       br_if 3, {{[^,]+}}{{$}}
 ; OPT-NOT:   block
 ; OPT:       br_if 2, {{[^,]+}}{{$}}
 ; OPT-NOT:   block
 ; OPT:       br_if 0, {{[^,]+}}{{$}}
 ; OPT-NEXT:  end_loop{{$}}
 ; OPT-NOT:   block
second:
   ret void
 }
 
 ; Test a case where there are multiple backedges and multiple loop exits
 ; that end in unreachable.
 
 ; CHECK-LABEL: test7:
 ; CHECK:       .LBB16_1:
-; CHECK-NEXT:  loop{{$}}
+; CHECK-NEXT:  loop    {{$}}
 ; CHECK-NOT:   block
-; CHECK:       block{{$}}
+; CHECK:       block   {{$}}
 ; CHECK:       br_if 0, {{[^,]+}}{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       br_if 1, {{[^,]+}}{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       unreachable
 ; CHECK-NEXT:  .LBB16_4:
 ; CHECK-NEXT:  end_block{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       br_if 0, {{[^,]+}}{{$}}
 ; CHECK-NEXT:  end_loop{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       unreachable
 ; OPT-LABEL: test7:
 ; OPT:       .LBB16_1:
 ; OPT-NEXT:  block
-; OPT-NEXT:  loop{{$}}
+; OPT-NEXT:  loop    {{$}}
 ; OPT-NOT:   block
-; OPT:       block{{$}}
+; OPT:       block   {{$}}
 ; OPT-NOT:   block
 ; OPT:       br_if 0, {{[^,]+}}{{$}}
 ; OPT-NOT:   block
 ; OPT:       br_if 1, {{[^,]+}}{{$}}
 ; OPT:       br 3{{$}}
 ; OPT-NEXT:  .LBB16_3:
 ; OPT-NEXT:  end_block
 ; OPT-NOT:   block
u1:
   store volatile i32 5, i32* null
   unreachable
 }
 
 ; Test an interesting case using nested loops and switches.
 
 ; CHECK-LABEL: test8:
 ; CHECK:       .LBB17_1:
-; CHECK-NEXT:  loop{{$}}
+; CHECK-NEXT:  loop i32{{$}}
 ; CHECK-NEXT:  i32.const $push{{[^,]+}}, 0{{$}}
 ; CHECK-NEXT:  br_if    0, {{[^,]+}}{{$}}
 ; CHECK-NEXT:  br       0{{$}}
 ; CHECK-NEXT:  .LBB17_2:
 ; CHECK-NEXT:  end_loop{{$}}
 ; OPT-LABEL: test8:
 ; OPT:       .LBB17_1:
-; OPT-NEXT:  loop{{$}}
+; OPT-NEXT:  loop i32{{$}}
 ; OPT-NEXT:  i32.const $push{{[^,]+}}, 0{{$}}
 ; OPT-NEXT:  br_if    0, {{[^,]+}}{{$}}
 ; OPT-NEXT:  br       0{{$}}
 ; OPT-NEXT:  .LBB17_2:
 ; OPT-NEXT:  end_loop{{$}}
-define void @test8() {
+define i32 @test8() {
 bb:
   br label %bb1
 
 bb1:
   br i1 undef, label %bb2, label %bb3
 
 bb2:
   switch i8 undef, label %bb1 [
     i8 44, label %bb2
   ]
 
 bb3:
   switch i8 undef, label %bb1 [
     i8 44, label %bb2
   ]
 }
 
 ; Test an interesting case using nested loops that share a bottom block.
 
 ; CHECK-LABEL: test9:
 ; CHECK:       .LBB18_1:
-; CHECK-NEXT:  loop{{$}}
+; CHECK-NEXT:  loop    {{$}}
 ; CHECK-NOT:   block
 ; CHECK:       br_if     1, {{[^,]+}}{{$}}
 ; CHECK-NEXT:  .LBB18_2:
-; CHECK-NEXT:  loop{{$}}
+; CHECK-NEXT:  loop    {{$}}
 ; CHECK-NOT:   block
-; CHECK:       block{{$}}
+; CHECK:       block   {{$}}
 ; CHECK-NOT:   block
 ; CHECK:       br_if     0, {{[^,]+}}{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       br_if     3, {{[^,]+}}{{$}}
 ; CHECK-NEXT:  br        1{{$}}
 ; CHECK-NEXT:  .LBB18_4:
 ; CHECK-NEXT:  end_block{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       br_if     2, {{[^,]+}}{{$}}
 ; CHECK-NEXT:  br        0{{$}}
 ; CHECK-NEXT:  .LBB18_5:
 ; CHECK-NOT:   block
 ; CHECK:       return{{$}}
 ; OPT-LABEL: test9:
 ; OPT:       .LBB18_1:
-; OPT-NEXT:  loop{{$}}
+; OPT-NEXT:  loop    {{$}}
 ; OPT-NOT:   block
 ; OPT:       br_if     1, {{[^,]+}}{{$}}
 ; OPT-NEXT:  .LBB18_2:
-; OPT-NEXT:  loop{{$}}
+; OPT-NEXT:  loop    {{$}}
 ; OPT-NOT:   block
-; OPT:       block{{$}}
+; OPT:       block   {{$}}
 ; OPT-NOT:   block
 ; OPT:       br_if     0, {{[^,]+}}{{$}}
 ; OPT-NOT:   block
 ; OPT:       br_if     1, {{[^,]+}}{{$}}
 ; OPT-NEXT:  br        3{{$}}
 ; OPT-NEXT:  .LBB18_4:
 ; OPT-NEXT:  end_block{{$}}
 ; OPT-NOT:   block
end:
   ret void
 }
 
 ; Test an interesting case involving nested loops sharing a loop bottom,
 ; and loop exits to a block with unreachable.
 
 ; CHECK-LABEL: test10:
 ; CHECK:       .LBB19_1:
-; CHECK-NEXT:  loop{{$}}
+; CHECK-NEXT:  loop    {{$}}
 ; CHECK-NOT:   block
 ; CHECK:       br_if    0, {{[^,]+}}{{$}}
 ; CHECK:       .LBB19_3:
-; CHECK-NEXT:  block{{$}}
-; CHECK-NEXT:  loop{{$}}
+; CHECK-NEXT:  block   {{$}}
+; CHECK-NEXT:  loop    {{$}}
 ; CHECK-NOT:   block
 ; CHECK:       .LBB19_4:
-; CHECK-NEXT:  loop{{$}}
+; CHECK-NEXT:  loop    {{$}}
 ; CHECK-NOT:   block
 ; CHECK:       br_if    5, {{[^,]+}}{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       br_table  {{[^,]+}}, 0, 1, 5, 2, 4, 0{{$}}
 ; CHECK-NEXT:  .LBB19_6:
 ; CHECK-NEXT:  end_loop{{$}}
 ; CHECK-NEXT:  end_loop{{$}}
 ; CHECK-NEXT:  return{{$}}
 ; CHECK-NEXT:  .LBB19_7:
 ; CHECK-NEXT:  end_block{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       br       0{{$}}
 ; CHECK-NEXT:  .LBB19_8:
 ; OPT-LABEL: test10:
 ; OPT:       .LBB19_1:
-; OPT-NEXT:  loop{{$}}
+; OPT-NEXT:  loop    {{$}}
 ; OPT-NOT:   block
 ; OPT:       br_if    0, {{[^,]+}}{{$}}
 ; OPT:       .LBB19_3:
-; OPT-NEXT:  block{{$}}
-; OPT-NEXT:  loop{{$}}
+; OPT-NEXT:  block   {{$}}
+; OPT-NEXT:  loop    {{$}}
 ; OPT-NOT:   block
 ; OPT:       .LBB19_4:
-; OPT-NEXT:  loop{{$}}
+; OPT-NEXT:  loop    {{$}}
 ; OPT-NOT:   block
 ; OPT:       br_if    5, {{[^,]+}}{{$}}
 ; OPT-NOT:   block
 ; OPT:       br_table  {{[^,]+}}, 0, 1, 5, 2, 4, 0{{$}}
 ; OPT-NEXT:  .LBB19_6:
 ; OPT-NEXT:  end_loop{{$}}
 ; OPT-NEXT:  end_loop{{$}}
 ; OPT-NEXT:  return{{$}}

 
 bb6:
   ret void
 }
 
 ; Test a CFG DAG with interesting merging.
 
 ; CHECK-LABEL: test11:
-; CHECK:       block{{$}}
-; CHECK-NEXT:  block{{$}}
-; CHECK-NEXT:  block{{$}}
-; CHECK-NEXT:  block{{$}}
+; CHECK:       block   {{$}}
+; CHECK-NEXT:  block   {{$}}
+; CHECK-NEXT:  block   {{$}}
+; CHECK-NEXT:  block   {{$}}
 ; CHECK:       br_if        0, {{[^,]+}}{{$}}
 ; CHECK-NOT:   block
-; CHECK:       block{{$}}
+; CHECK:       block   {{$}}
 ; CHECK-NEXT:  i32.const
 ; CHECK-NEXT:  br_if        0, {{[^,]+}}{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       br_if        2, {{[^,]+}}{{$}}
 ; CHECK-NEXT:  .LBB20_3:
 ; CHECK-NEXT:  end_block{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       return{{$}}

 ; CHECK-NEXT:  end_block{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       return{{$}}
 ; CHECK-NEXT:  .LBB20_8:
 ; CHECK-NEXT:  end_block{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       return{{$}}
 ; OPT-LABEL: test11:
-; OPT:       block{{$}}
-; OPT-NEXT:  block{{$}}
+; OPT:       block   {{$}}
+; OPT-NEXT:  block   {{$}}
 ; OPT:       br_if        0, $pop{{[0-9]+}}{{$}}
 ; OPT-NOT:   block
-; OPT:       block{{$}}
+; OPT:       block   {{$}}
 ; OPT-NEXT:  i32.const
 ; OPT-NEXT:  br_if        0, {{[^,]+}}{{$}}
 ; OPT-NOT:   block
 ; OPT:       br_if        2, {{[^,]+}}{{$}}
 ; OPT-NEXT:  .LBB20_3:
 ; OPT-NEXT:  end_block{{$}}
 ; OPT-NOT:   block
 ; OPT:       return{{$}}
 ; OPT-NEXT:  .LBB20_4:
 ; OPT-NEXT:  end_block{{$}}
 ; OPT-NOT:   block
-; OPT:       block{{$}}
+; OPT:       block   {{$}}
 ; OPT-NOT:   block
 ; OPT:       br_if        0, $pop{{[0-9]+}}{{$}}
 ; OPT-NOT:   block
 ; OPT:       return{{$}}
 ; OPT-NEXT:  .LBB20_6:
 ; OPT-NEXT:  end_block{{$}}
 ; OPT-NOT:   block
 ; OPT:       br_if        0, $pop{{[0-9]+}}{{$}}
bb7:
   ret void
 bb8:
   store volatile i32 8, i32* null
   ret void
 }
 
 ; CHECK-LABEL: test12:
 ; CHECK:       .LBB21_1:
-; CHECK-NEXT:  loop{{$}}
+; CHECK-NEXT:  loop    {{$}}
 ; CHECK-NOT:   block
-; CHECK:       block{{$}}
-; CHECK-NEXT:  block{{$}}
+; CHECK:       block   {{$}}
+; CHECK-NEXT:  block   {{$}}
 ; CHECK:       br_if       0, {{[^,]+}}{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       br_if       1, {{[^,]+}}{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       br_if       1, {{[^,]+}}{{$}}
 ; CHECK-NEXT:  br          3{{$}}
 ; CHECK-NEXT:  .LBB21_4:
 ; CHECK-NEXT:  end_block{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       br_if       0, {{[^,]+}}{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       br_if       2, {{[^,]+}}{{$}}
 ; CHECK-NEXT:  .LBB21_6:
 ; CHECK-NEXT:  end_block{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       br          0{{$}}
 ; CHECK-NEXT:  .LBB21_7:
 ; CHECK-NEXT:  end_loop{{$}}
 ; CHECK-NEXT:  return{{$}}
 ; OPT-LABEL: test12:
 ; OPT:       .LBB21_1:
-; OPT-NEXT:  loop{{$}}
+; OPT-NEXT:  loop    {{$}}
 ; OPT-NOT:   block
-; OPT:       block{{$}}
-; OPT-NEXT:  block{{$}}
+; OPT:       block   {{$}}
+; OPT-NEXT:  block   {{$}}
 ; OPT:       br_if       0, {{[^,]+}}{{$}}
 ; OPT-NOT:   block
 ; OPT:       br_if       1, {{[^,]+}}{{$}}
 ; OPT-NOT:   block
 ; OPT:       br_if       1, {{[^,]+}}{{$}}
 ; OPT-NEXT:  br          3{{$}}
 ; OPT-NEXT:  .LBB21_4:
 ; OPT-NEXT:  end_block{{$}}

 }
 
 ; A block can be "branched to" from another even if it is also reachable via
 ; fallthrough from the other. This would normally be optimized away, so use
 ; optnone to disable optimizations to test this case.
 
 ; CHECK-LABEL: test13:
 ; CHECK-NEXT:  .local i32{{$}}
-; CHECK-NEXT:  block{{$}}
-; CHECK-NEXT:  block{{$}}
+; CHECK-NEXT:  block   {{$}}
+; CHECK-NEXT:  block   {{$}}
 ; CHECK:       br_if 0, $pop0{{$}}
-; CHECK:       block{{$}}
+; CHECK:       block   {{$}}
 ; CHECK:       br_if 0, $pop3{{$}}
 ; CHECK:       .LBB22_3:
 ; CHECK-NEXT:  end_block{{$}}
 ; CHECK:       br_if 1, $pop{{[0-9]+}}{{$}}
 ; CHECK-NEXT:  br 1{{$}}
 ; CHECK-NEXT:  .LBB22_4:
 ; CHECK-NEXT:  end_block{{$}}
 ; CHECK-NEXT:  return{{$}}
 ; CHECK-NEXT:  .LBB22_5:
 ; CHECK-NEXT:  end_block{{$}}
 ; CHECK-NEXT:  unreachable{{$}}
 ; OPT-LABEL: test13:
 ; OPT-NEXT:  .local i32{{$}}
-; OPT-NEXT:  block{{$}}
-; OPT-NEXT:  block{{$}}
+; OPT-NEXT:  block   {{$}}
+; OPT-NEXT:  block   {{$}}
 ; OPT:       br_if 0, $pop0{{$}}
-; OPT:       block{{$}}
+; OPT:       block   {{$}}
 ; OPT:       br_if 0, $pop3{{$}}
 ; OPT:       .LBB22_3:
 ; OPT-NEXT:  end_block{{$}}
 ; OPT:       br_if 1, $pop{{[0-9]+}}{{$}}
 ; OPT-NEXT:  br 1{{$}}
 ; OPT-NEXT:  .LBB22_4:
 ; OPT-NEXT:  end_block
 ; OPT-NEXT:  return

 }
 
 ; Test a case with a single-block loop that has another loop
 ; as a successor. The end_loop for the first loop should go
 ; before the loop for the second.
 
 ; CHECK-LABEL: test14:
 ; CHECK-NEXT: .LBB23_1:{{$}}
-; CHECK-NEXT:     loop{{$}}
+; CHECK-NEXT:     loop    {{$}}
 ; CHECK-NEXT:     i32.const   $push0=, 0{{$}}
 ; CHECK-NEXT:     br_if       0, $pop0{{$}}
 ; CHECK-NEXT:     end_loop{{$}}
 ; CHECK-NEXT: .LBB23_3:{{$}}
-; CHECK-NEXT:     loop{{$}}
+; CHECK-NEXT:     loop    {{$}}
 ; CHECK-NEXT:     i32.const   $push1=, 0{{$}}
 ; CHECK-NEXT:     br_if       0, $pop1{{$}}
 ; CHECK-NEXT:     end_loop{{$}}
 ; CHECK-NEXT:     return{{$}}
 define void @test14() {
 bb:
   br label %bb1
 

 ; Test that a block boundary which ends one block, begins another block, and
 ; also begins a loop, has the markers placed in the correct order.
 
 ; CHECK-LABEL: test15:
 ; CHECK:        block
 ; CHECK-NEXT:   block
 ; CHECK:        br_if       0, $pop{{.*}}{{$}}
 ; CHECK:        .LBB24_2:
-; CHECK-NEXT:   block{{$}}
-; CHECK-NEXT:   loop{{$}}
+; CHECK-NEXT:   block   {{$}}
+; CHECK-NEXT:   loop    {{$}}
 ; CHECK:        br_if       1, $pop{{.*}}{{$}}
 ; CHECK:        br_if       0, ${{.*}}{{$}}
 ; CHECK-NEXT:   br          2{{$}}
 ; CHECK-NEXT:   .LBB24_4:
 ; CHECK-NEXT:   end_loop{{$}}
 ; CHECK:        .LBB24_5:
 ; CHECK-NEXT:   end_block{{$}}
 ; CHECK:        br_if       1, $pop{{.*}}{{$}}

test/CodeGen/WebAssembly/reg-stackify.ll

 ; Don't schedule stack uses into the stack. To reduce register pressure, the
 ; scheduler might be tempted to move the definition of $2 down. However, this
 ; would risk getting incorrect liveness if the instructions are later
 ; rearranged to make the stack contiguous.
 
 ; CHECK-LABEL: stack_uses:
 ; CHECK: .param i32, i32, i32, i32{{$}}
 ; CHECK-NEXT: .result i32{{$}}
-; CHECK-NEXT: block{{$}}
+; CHECK-NEXT: block   {{$}}
 ; CHECK-NEXT: i32.const   $push[[L13:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.lt_s    $push[[L0:[0-9]+]]=, $0, $pop[[L13]]{{$}}
 ; CHECK-NEXT: i32.const   $push[[L1:[0-9]+]]=, 2{{$}}
 ; CHECK-NEXT: i32.lt_s    $push[[L2:[0-9]+]]=, $1, $pop[[L1]]{{$}}
 ; CHECK-NEXT: i32.xor     $push[[L5:[0-9]+]]=, $pop[[L0]], $pop[[L2]]{{$}}
 ; CHECK-NEXT: i32.const   $push[[L12:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.lt_s    $push[[L3:[0-9]+]]=, $2, $pop[[L12]]{{$}}
 ; CHECK-NEXT: i32.const   $push[[L11:[0-9]+]]=, 2{{$}}

 }
 
 ; Test an interesting case where the load has multiple uses and cannot
 ; be trivially stackified. However, it can be stackified with a tee_local.
 
 ; CHECK-LABEL: multiple_uses:
 ; CHECK: .param       i32, i32, i32{{$}}
 ; CHECK-NEXT: .local       i32{{$}}
-; CHECK-NEXT: block{{$}}
+; CHECK-NEXT: block   {{$}}
 ; CHECK-NEXT: i32.load    $push[[NUM0:[0-9]+]]=, 0($2){{$}}
 ; CHECK-NEXT: tee_local   $push[[NUM1:[0-9]+]]=, $3=, $pop[[NUM0]]{{$}}
 ; CHECK-NEXT: i32.ge_u    $push[[NUM2:[0-9]+]]=, $pop[[NUM1]], $1{{$}}
 ; CHECK-NEXT: br_if       0, $pop[[NUM2]]{{$}}
 ; CHECK-NEXT: i32.lt_u    $push[[NUM3:[0-9]+]]=, $3, $0{{$}}
 ; CHECK-NEXT: br_if       0, $pop[[NUM3]]{{$}}
 ; CHECK-NEXT: i32.store   $drop=, 0($2), $3{{$}}
 ; CHECK-NEXT: .LBB8_3:

test/CodeGen/WebAssembly/switch.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-block-placement -verify-machineinstrs | FileCheck %s
 
 ; Test switch instructions. Block placement is disabled because it reorders
 ; the blocks in a way that isn't interesting here.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare void @foo0()
 declare void @foo1()
 declare void @foo2()
 declare void @foo3()
 declare void @foo4()
 declare void @foo5()
 
 ; CHECK-LABEL: bar32:
-; CHECK: block{{$}}
-; CHECK: block{{$}}
-; CHECK: block{{$}}
-; CHECK: block{{$}}
-; CHECK: block{{$}}
-; CHECK: block{{$}}
-; CHECK: block{{$}}
+; CHECK: block   {{$}}
+; CHECK: block   {{$}}
+; CHECK: block   {{$}}
+; CHECK: block   {{$}}
+; CHECK: block   {{$}}
+; CHECK: block   {{$}}
+; CHECK: block   {{$}}
 ; CHECK: br_table {{[^,]+}}, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 4, 5, 0{{$}}
 ; CHECK: .LBB0_2:
 ; CHECK:   call foo0@FUNCTION{{$}}
 ; CHECK: .LBB0_3:
 ; CHECK:   call foo1@FUNCTION{{$}}
 ; CHECK: .LBB0_4:
 ; CHECK:   call foo2@FUNCTION{{$}}
 ; CHECK: .LBB0_5:
sw.bb.5:                                          ; preds = %entry
   tail call void @foo5()
   br label %sw.epilog
 
 sw.epilog:                                        ; preds = %entry, %sw.bb.5, %sw.bb.4, %sw.bb.3, %sw.bb.2, %sw.bb.1, %sw.bb
   ret void
 }
 
 ; CHECK-LABEL: bar64:
-; CHECK: block{{$}}
-; CHECK: block{{$}}
-; CHECK: block{{$}}
-; CHECK: block{{$}}
-; CHECK: block{{$}}
-; CHECK: block{{$}}
-; CHECK: block{{$}}
+; CHECK: block   {{$}}
+; CHECK: block   {{$}}
+; CHECK: block   {{$}}
+; CHECK: block   {{$}}
+; CHECK: block   {{$}}
+; CHECK: block   {{$}}
+; CHECK: block   {{$}}
 ; CHECK: br_table {{[^,]+}}, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 4, 5, 0{{$}}
 ; CHECK: .LBB1_2:
 ; CHECK:   call foo0@FUNCTION{{$}}
 ; CHECK: .LBB1_3:
 ; CHECK:   call foo1@FUNCTION{{$}}
 ; CHECK: .LBB1_4:
 ; CHECK:   call foo2@FUNCTION{{$}}
 ; CHECK: .LBB1_5: