Don't randomly encode %rip where illegal

[dougk]

handle Intel syntax also

[niravd]

The patch is missing the intel syntax tests cases. Otherwise LGTM.

[dougk]

test Intel syntax

llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp

 
 /// }
 
 static bool CheckBaseRegAndIndexReg(unsigned BaseReg, unsigned IndexReg,
                                     StringRef &ErrMsg) {
   // If we have both a base register and an index register make sure they are
   // both 64-bit or 32-bit registers.
   // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
+
+  if ((BaseReg == X86::RIP && IndexReg != 0) || (IndexReg == X86::RIP)) {
+    ErrMsg = "invalid base+index expression";
+    return true;
+  }
   if (BaseReg != 0 && IndexReg != 0) {
     if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
         (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
          X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) &&
         IndexReg != X86::RIZ) {
       ErrMsg = "base register is 64-bit, but index register is not";
       return true;
     }
if (getSTI().getFeatureBits()[X86::FeatureAVX512] &&
     return ParseRoundingModeOp(Start, End);
 
   // Register.
   unsigned RegNo = 0;
   if (getLexer().is(AsmToken::Identifier) &&
       !ParseRegister(RegNo, Start, End)) {
     // If this is a segment register followed by a ':', then this is the start
     // of a segment override, otherwise this is a normal register reference.
-    // In case it is a normal register and there is ptr in the operand this 
+    // In case it is a normal register and there is ptr in the operand this
     // is an error
-    if (getLexer().isNot(AsmToken::Colon)){
-      if (PtrInOperand){
+    if (RegNo == X86::RIP)
+      return ErrorOperand(Start, "rip can only be used as a base register");
+    if (getLexer().isNot(AsmToken::Colon)) {
+      if (PtrInOperand) {
         return ErrorOperand(Start, "expected memory operand after "
                                    "'ptr', found register operand instead");
       }
       return X86Operand::CreateReg(RegNo, Start, End);
     }
     return ParseIntelSegmentOverride(/*SegReg=*/RegNo, Start, Size);
   }
 
case AsmToken::Percent: {
     unsigned RegNo;
     SMLoc Start, End;
     if (ParseRegister(RegNo, Start, End)) return nullptr;
     if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
       Error(Start, "%eiz and %riz can only be used as index registers",
             SMRange(Start, End));
       return nullptr;
     }
+    if (RegNo == X86::RIP) {
+      Error(Start, "%rip can only be used as a base register",
+            SMRange(Start, End));
+      return nullptr;
+    }
 
     // If this is a segment register followed by a ':', then this is the start
     // of a memory reference, otherwise this is a normal register reference.
     if (getLexer().isNot(AsmToken::Colon))
       return X86Operand::CreateReg(RegNo, Start, End);
 
     if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo))
       return ErrorOperand(Start, "invalid segment register");
if (getLexer().is(AsmToken::Comma)) {
     // Following the comma we should have either an index register, or a scale
     // value. We don't support the later form, but we want to parse it
     // correctly.
     //
     // Not that even though it would be completely consistent to support syntax
     // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
     if (getLexer().is(AsmToken::Percent)) {
       SMLoc L;
-      if (ParseRegister(IndexReg, L, L)) return nullptr;
+      if (ParseRegister(IndexReg, L, L))
+        return nullptr;
+      if (BaseReg == X86::RIP) {
+        Error(IndexLoc, "%rip as base register can not have an index register");
+        return nullptr;
+      }
+      if (IndexReg == X86::RIP) {
+        Error(IndexLoc, "%rip is not allowed as an index register");
+        return nullptr;
+      }
 
       if (getLexer().isNot(AsmToken::RParen)) {
         // Parse the scale amount:
         //  ::= ',' [scale-expression]
         if (getLexer().isNot(AsmToken::Comma)) {
           Error(Parser.getTok().getLoc(),
                 "expected comma in scale expression");
           return nullptr;

llvm/trunk/lib/Target/X86/X86RegisterInfo.td

 
 def GR32 : RegisterClass<"X86", [i32], 32,
                          (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
                               R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D)>;
 
 // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
 // RIP isn't really a register and it can't be used anywhere except in an
 // address, but it doesn't cause trouble.
+// FIXME: it *does* cause trouble - CheckBaseRegAndIndexReg() has extra
+// tests because of the inclusion of RIP in this register class.
 def GR64 : RegisterClass<"X86", [i64], 64,
                          (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
                               RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
 
 // Segment registers for use by MOV instructions (and others) that have a
 //   segment register as one operand.  Always contain a 16-bit segment
 //   descriptor.
 def SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>;

llvm/trunk/test/MC/X86/intel-syntax-error.s

 .global i
 .set FOO, 2
 //CHECK: error: cannot use base register with variable reference
 mov eax, DWORD PTR arr[ebp + 1 + (2 * 5) - 3 + 1<<1]
 //CHECK: error: cannot use index register with variable reference
 mov eax, DWORD PTR arr[esi*4]
 //CHECK: error: cannot use more than one symbol in memory operand
 mov eax, DWORD PTR arr[i]
+//CHECK: error: rip can only be used as a base register
+.code64
+mov rax, rip
+//CHECK: error: invalid base+index expression
+mov rbx, [rax+rip]

llvm/trunk/test/MC/X86/x86_errors.s

 // 64: error: instruction requires: Not 64-bit mode
 jcxz 1
 
 // 32: error: register %cr8 is only available in 64-bit mode
 movl %edx, %cr8
 
 // 32: error: register %dr8 is only available in 64-bit mode
 movl %edx, %dr8
+
+// 32: error: register %rip is only available in 64-bit mode
+// 64: error: %rip can only be used as a base register
+mov %rip, %rax
+
+// 32: error: register %rax is only available in 64-bit mode
+// 64: error: %rip is not allowed as an index register
+mov (%rax,%rip), %rbx