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Differential D24443

[AVX512] Fix pattern for vgetmantsd instruction
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Authored by igorb on Sep 11 2016, 4:32 AM.

Details

Reviewers
guyblank
AsafBadouh
delena
Commits
rGe73ef85c6f09: [AVX512] Fix pattern for vgetmantsd and all other instructions that use same…
rL281164: [AVX512] Fix pattern for vgetmantsd and all other instructions that use same…
Summary

Fix pattern for vgetmantsd and all other instructions that use same class. Fix memory operand size, remove unnecessary pattern.

Diff Detail

Repository
rL LLVM

Event Timeline

igorb updated this revision to Diff 70962.Sep 11 2016, 4:32 AM
igorb retitled this revision from to [AVX512] Fix pattern for vgetmantsd instruction.
igorb updated this object.
igorb added reviewers: delena, AsafBadouh, guyblank.
igorb set the repository for this revision to rL LLVM.
igorb added a subscriber: llvm-commits.
AsafBadouh accepted this revision.Sep 11 2016, 4:50 AM
AsafBadouh edited edge metadata.

LGTM

This revision is now accepted and ready to land.Sep 11 2016, 4:50 AM
Closed by commit rL281164: [AVX512] Fix pattern for vgetmantsd and all other instructions that use same… (authored by ibreger). · Explain WhySep 11 2016, 5:47 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
X86/
9 lines

Diff 70963

llvm/trunk/lib/Target/X86/X86InstrAVX512.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,581 Lines • ▼ Show 20 Linesmulticlass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst), defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
(ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3", OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
(OpNode (_.VT _.RC:$src1), (OpNode (_.VT _.RC:$src1),
(_.VT _.RC:$src2), (_.VT _.RC:$src2),
(i32 imm:$src3), (i32 imm:$src3),
(i32 FROUND_CURRENT))>; (i32 FROUND_CURRENT))>;
defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst), defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
(ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3", OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
(OpNode (_.VT _.RC:$src1), (OpNode (_.VT _.RC:$src1),
(_.VT (scalar_to_vector (_.VT (scalar_to_vector
(_.ScalarLdFrag addr:$src2))), (_.ScalarLdFrag addr:$src2))),
(i32 imm:$src3), (i32 imm:$src3),
(i32 FROUND_CURRENT))>; (i32 FROUND_CURRENT))>;
let isAsmParserOnly = 1, mayLoad = 1, hasSideEffects = 0 in {
defm rmi_alt :AVX512_maskable_in_asm<opc, MRMSrcMem, _, (outs _.FRC:$dst),
(ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
[]>;
}
} }
} }
//handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae} //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr, multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
SDNode OpNode, X86VectorVTInfo _>{ SDNode OpNode, X86VectorVTInfo _>{
let ExeDomain = _.ExeDomain in let ExeDomain = _.ExeDomain in
defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst), defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
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