[mips] Add IAS support for dvp, evp

[sdardis]

Summary

These instructions were only defined for microMIPSR6 previously. Add
definitions for MIPSR6, correct definitions for microMIPSR6, flag these
instructions as having unmodelled side effects (they disable/enable
virtual processors) and add missing disassember tests for microMIPSR6.

[vkalintiris]

LGTM with a few minor changes, see inline comments.

lib/Target/Mips/MicroMips32r6InstrInfo.td

1351

I believe that this should be an out operand.

lib/Target/Mips/Mips32r6InstrFormats.td

48

I don't think that we need the _DVPEVP suffix because we might need the COP0 opcode group again in the future.

lib/Target/Mips/Mips32r6InstrInfo.td

911–912

Can you add tests for the aliases too?

[Eugene.Zelenko]

Looks like patch was not committed.

[sdardis]

Thanks, committed as r284115.

lib/Target/Mips/MicroMips32r6InstrInfo.td

1351

Yes, you're correct there.

lib/Target/Mips/Mips32r6InstrFormats.td

48

Rechecking the .td files shows that OPGROUP_COP0 was defined in MipsEVAInstrFormats.td. I've renamed the def there to OPGROUP_COP0_TLB. At some point we will want to refactor the format files.

lib/Target/Mips/MicroMips32r6InstrInfo.td

class TLBINV_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> {
   string AsmString = opstr;
   list<dag> Pattern = [];
   InstrItinClass Itinerary = Itin;
 }
 
 class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv", II_TLBINV>;
 class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf", II_TLBINVF>;
 
-class DVPEVP_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> {
+class EVP_MMR6_DESC_BASE {
   dag OutOperandList = (outs);
   dag InOperandList = (ins GPR32Opnd:$rs);
-  string AsmString = !strconcat(opstr, "\t$rs");
+  string AsmString = "evp\t$rs";
   list<dag> Pattern = [];
-  InstrItinClass Itinerary = Itin;
+  InstrItinClass Itinerary = II_EVP;
+  bit hasUnModeledSideEffects = 1;
+}
+
+class DVP_MMR6_DESC_BASE {
+  dag OutOperandList = (outs GPR32Opnd:$rs);
+  dag InOperandList = (ins);
+  string AsmString = "dvp\t$rs";
+  list<dag> Pattern = [];
+  InstrItinClass Itinerary = II_DVP;
+  bit hasUnModeledSideEffects = 1;
 }
 
-class DVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"dvp", II_DVP>;
-class EVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"evp", II_EVP>;
+class DVP_MMR6_DESC : DVP_MMR6_DESC_BASE;
+class EVP_MMR6_DESC : EVP_MMR6_DESC_BASE;
 
 class BEQZC_MMR6_DESC
     : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21_mm, GPR32Opnd>,
       MMR6Arch<"beqzc">;
 class BNEZC_MMR6_DESC
     : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21_mm, GPR32Opnd>,
       MMR6Arch<"bnezc">;
 

lib/Target/Mips/Mips32r6InstrFormats.td

 //
 // Field Values
 //
 //===----------------------------------------------------------------------===//
 
 class OPGROUP<bits<6> Val> {
   bits<6> Value = Val;
 }
+def OPGROUP_COP0_DVPEVP : OPGROUP<0b010000>;
 def OPGROUP_COP1     : OPGROUP<0b010001>;
 def OPGROUP_COP2     : OPGROUP<0b010010>;
 def OPGROUP_ADDI     : OPGROUP<0b001000>;
 def OPGROUP_AUI      : OPGROUP<0b001111>;
 def OPGROUP_BLEZ     : OPGROUP<0b000110>;
 def OPGROUP_BGTZ     : OPGROUP<0b000111>;
 def OPGROUP_BLEZL    : OPGROUP<0b010110>;
 def OPGROUP_BGTZL    : OPGROUP<0b010111>;
class BAL_FM : MipsR6Inst {
   bits<32> Inst;
 
   let Inst{31-26} = OPGROUP_REGIMM.Value;
   let Inst{25-21} = 0b00000;
   let Inst{20-16} = OPCODE5_BGEZAL.Value;
   let Inst{15-0} = offset;
 }
 
+class COP0_EVP_DVP_FM<bits<1> sc> : MipsR6Inst {
+  bits<5> rt;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = OPGROUP_COP0_DVPEVP.Value;
+  let Inst{25-21} = 0b01011;
+  let Inst{20-16} = rt;
+  let Inst{15-11} = 0b00000;
+  let Inst{10-6}  = 0b00000;
+  let Inst{5}     = sc;
+  let Inst{4-3}   = 0b00;
+  let Inst{2-0}   = 0b100;
+}
+
 class COP1_2R_FM<bits<6> funct, FIELD_FMT Format> : MipsR6Inst {
   bits<5> fs;
   bits<5> fd;
 
   bits<32> Inst;
 
   let Inst{31-26} = OPGROUP_COP1.Value;
   let Inst{25-21} = Format.Value;

lib/Target/Mips/Mips32r6InstrInfo.td

class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>,
                     DecodeDisambiguates<"BlezGroupBranch">;
 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
 
 class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>;
 class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>;
 class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>;
 class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>;
 
+class DVP_ENC : COP0_EVP_DVP_FM<0b1>;
+class EVP_ENC : COP0_EVP_DVP_FM<0b0>;
+
 class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;
 class JIC_ENC   : JMP_IDX_COMPACT_FM<0b110110>;
 class JR_HB_R6_ENC : JR_HB_R6_FM<OPCODE6_JALR>;
 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
 class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>,
                     DecodeDisambiguatedBy<"BlezGroupBranch">;
 class BNVC_ENC   : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
                    DecodeDisambiguatedBy<"DaddiGroupBranch">;
class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
   list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
   InstrItinClass Itinerary = itin;
   // This instruction doesn't trap division by zero itself. We must insert
   // teq instructions as well.
   bit usesCustomInserter = 1;
 }
 
+class DVP_DESC : MipsR6Arch<"dvp"> {
+  dag OutOperandList = (outs GPR32Opnd:$rt);
+  dag InOperandList = (ins);
+  string AsmString = "dvp\t$rt";
+  list<dag> Pattern = [];
+  InstrItinClass Itinerary = II_DVP;
+  bit hasUnModeledSideEffects = 1;
+}
+
+class EVP_DESC : MipsR6Arch<"evp"> {
+  dag OutOperandList = (outs GPR32Opnd:$rt);
+  dag InOperandList = (ins);
+  string AsmString = "evp\t$rt";
+  list<dag> Pattern = [];
+  InstrItinClass Itinerary = II_EVP;
+  bit hasUnModeledSideEffects = 1;
+}
+
 class DIV_DESC  : DIVMOD_DESC_BASE<"div", GPR32Opnd, II_DIV, sdiv>;
 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, II_DIVU, udiv>;
 class MOD_DESC  : DIVMOD_DESC_BASE<"mod", GPR32Opnd, II_MOD, srem>;
 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, II_MODU, urem>;
 
 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
   list<Register> Defs = [RA];
 }

 def CLO_R6 : R6MMR6Rel, CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6;
 def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;
 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd, II_CMP_CC_S>;
 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd, II_CMP_CC_D>;
 let AdditionalPredicates = [NotInMicroMips] in {
   def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, ISA_MIPS32R6;
   def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
 }
+
+def DVP : R6MMR6Rel, DVP_ENC, DVP_DESC, ISA_MIPS32R6;
+def EVP : R6MMR6Rel, EVP_ENC, EVP_DESC, ISA_MIPS32R6;
+
 def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
 def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6;
 def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
 let AdditionalPredicates = [NotInMicroMips] in {
   def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
   def LL_R6 : LL_R6_ENC, LL_R6_DESC, PTR_32, ISA_MIPS32R6;
 }
 def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in {
   def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
 }
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Aliases
 //
 //===----------------------------------------------------------------------===//
-
+def : MipsInstAlias<"dvp", (DVP ZERO), 0>, ISA_MIPS32R6;
+def : MipsInstAlias<"evp", (EVP ZERO), 0>, ISA_MIPS32R6;
 let AdditionalPredicates = [NotInMicroMips] in {
 def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6;
 def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6, GPR_32;
 }
 
 def : MipsInstAlias<"jrc $rs", (JIC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
 
 let AdditionalPredicates = [NotInMicroMips] in {

test/MC/Disassembler/Mips/micromips32r6/valid.txt

 0x00 0x07 0x00 0x07 # CHECK: break 7
 0x00 0x07 0x01 0x47 # CHECK: break 7, 5
 0x20 0x25 0x60 0x08 # CHECK: cache 1, 8($5)
 0x01 0x65 0x4b 0x3c # CHECK: clo $11, $5
 0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp
 0x00 0x00 0xe3 0x7c # CHECK: deret
 0x00 0xa4 0x19 0x18 # CHECK: div $3, $4, $5
 0x00 0xa4 0x19 0x98 # CHECK: divu $3, $4, $5
+0x00 0x11 0x19 0x7c # CHECK: dvp $17
+0x00 0x00 0x19 0x7c # CHECK: dvp $zero
 0x00 0x00 0x18 0x00 # CHECK: ehb
 0x00 0x00 0x57 0x7c # CHECK: ei
 0x00 0x0a 0x57 0x7c # CHECK: ei $10
 0x00 0x00 0xf3 0x7c # CHECK: eret
 0x00 0x01 0xf3 0x7c # CHECK: eretnc
+0x00 0x10 0x39 0x7c # CHECK: evp $16
+0x00 0x00 0x39 0x7c # CHECK: evp $zero
 0x80 0x05 0x01 0x00 # CHECK: jialc $5, 256
 0xa0 0x05 0x01 0x00 # CHECK: jic $5, 256
 0x3c 0x44 0x00 0x08 # CHECK: lh $2, 8($4)
 0x60 0x82 0x6a 0x08 # CHECK: lhe $4, 8($2)
 0x34 0x82 0x00 0x08 # CHECK: lhu $4, 8($2)
 0x60 0x82 0x62 0x08 # CHECK: lhue $4, 8($2)
 0x60 0x44 0x30 0x08 # CHECK: ll $2, 8($4)
 0x20 0x44 0x50 0x08 # CHECK: lwm32 $16, $17, 8($4)

test/MC/Disassembler/Mips/micromips64r6/valid.txt

 0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8
 0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
 0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
 0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
 0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
 0x00 0x00 0xe3 0x7c # CHECK: deret
 0x00 0x00 0x47 0x7c # CHECK: di
 0x00 0x0f 0x47 0x7c # CHECK: di $15
+0x00 0x11 0x19 0x7c # CHECK: dvp $17
+0x00 0x00 0x19 0x7c # CHECK: dvp $zero
+0x00 0x10 0x39 0x7c # CHECK: evp $16
+0x00 0x00 0x39 0x7c # CHECK: evp $zero
 0x00 0x00 0x43 0x7c # CHECK: tlbinv
 0x00 0x00 0x53 0x7c # CHECK: tlbinvf
 0x58 0x82 0x20 0x34 # CHECK: dinsu $4, $2, 32, 5
 0x58 0x82 0x38 0xc4 # CHECK: dinsm $4, $2, 3, 5
 0x58 0x82 0x38 0xcc # CHECK: dins $4, $2, 3, 5
 0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9, 0
 0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9
 0x00 0x22 0x3a 0xfc # CHECK: mtc0 $1, $2, 7

test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt

 0x8d 0x18 0x84 0x46 # CHECK: cmp.sult.s $f2, $f3, $f4
 0x8d 0x18 0xa4 0x46 # CHECK: cmp.sult.d $f2, $f3, $f4
 0x8e 0x18 0x84 0x46 # CHECK: cmp.sle.s $f2, $f3, $f4
 0x8e 0x18 0xa4 0x46 # CHECK: cmp.sle.d $f2, $f3, $f4
 0x8f 0x18 0x84 0x46 # CHECK: cmp.sule.s $f2, $f3, $f4
 0x8f 0x18 0xa4 0x46 # CHECK: cmp.sule.d $f2, $f3, $f4
 0x00 0x60 0x7e 0x41 # CHECK: di $fp
 0x00 0x60 0x60 0x41 # CHECK: di
+0x24 0x00 0x71 0x41 # CHECK: dvp $17
+0x24 0x00 0x60 0x41 # CHECK: dvp $zero
 0x9a 0x10 0x64 0x00 # CHECK: div $2, $3, $4
 0x9b 0x10 0x64 0x00 # CHECK: divu $2, $3, $4
 0x20 0x60 0x6e 0x41 # CHECK: ei $14
 0x20 0x60 0x60 0x41 # CHECK: ei
+0x04 0x00 0x70 0x41 # CHECK: evp $16
+0x04 0x00 0x60 0x41 # CHECK: evp $zero
 0xc5 0x10 0x64 0x00 # CHECK: lsa $2, $3, $4, 4
 0x43 0x00 0x48 0xec # CHECK: lwpc $2, 268
 0x43 0x00 0x50 0xec # CHECK: lwupc $2, 268
 0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1
 0xda 0x10 0x64 0x00 # CHECK: mod $2, $3, $4
 0xdb 0x10 0x64 0x00 # CHECK: modu $2, $3, $4
 0x98 0x10 0x64 0x00 # CHECK: mul $2, $3, $4
 0xd8 0x10 0x64 0x00 # CHECK: muh $2, $3, $4

test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt

 0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4
 0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4
 0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23
 0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x40 0x08 0x80 0x03 # CHECK: mfc0 $8, $16, 3
 0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x41 0x60 0x60 0x00 # CHECK: di
 0x41 0x60 0x60 0x20 # CHECK: ei
+0x41 0x60 0x00 0x24 # CHECK: dvp $zero
+0x41 0x60 0x00 0x04 # CHECK: evp $zero
 0x41 0x6e 0x60 0x20 # CHECK: ei $14
+0x41 0x70 0x00 0x04 # CHECK: evp $16
+0x41 0x71 0x00 0x24 # CHECK: dvp $17
 0x41 0x7e 0x60 0x00 # CHECK: di $fp
 # FIXME: The encode/decode functions are not inverses of each other.
 #        The immediate should be 4 but the disassembler currently emits 8
 0x45 0x20 0x00 0x01 # CHECK: bc1eqz $f0, 8
 # FIXME: The encode/decode functions are not inverses of each other.
 #        The immediate should be 4 but the disassembler currently emits 8
 0x45 0x3f 0x00 0x01 # CHECK: bc1eqz $f31, 8
 # FIXME: The encode/decode functions are not inverses of each other.

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt

 0x00 0x50 0x38 0x40 # CHECK: dmfc0 $24, $10, 0
 0xde 0x10 0x64 0x00 # CHECK: dmod $2, $3, $4
 0xdf 0x10 0x64 0x00 # CHECK: dmodu $2, $3, $4
 0x00 0x50 0xa4 0x40 # CHECK: dmtc0 $4, $10, 0
 0xdc 0x10 0x64 0x00 # CHECK: dmuh $2, $3, $4
 0xdd 0x10 0x64 0x00 # CHECK: dmuhu $2, $3, $4
 0x9c 0x10 0x64 0x00 # CHECK: dmul $2, $3, $4
 0x9d 0x10 0x64 0x00 # CHECK: dmulu $2, $3, $4
+0x24 0x00 0x71 0x41 # CHECK: dvp $17
+0x24 0x00 0x60 0x41 # CHECK: dvp $zero
 0x20 0x60 0x60 0x41 # CHECK: ei
 0x20 0x60 0x6e 0x41 # CHECK: ei $14
+0x04 0x00 0x70 0x41 # CHECK: evp $16
+0x04 0x00 0x60 0x41 # CHECK: evp $zero
 0x09 0xfc 0x80 0x00 # CHECK: jalr.hb $4
 0x09 0x24 0xa0 0x00 # CHECK: jalr.hb $4, $5
 0x00 0x00 0x19 0xf8 # CHECK: jalrc $25
 0x00 0x01 0x05 0xf8 # CHECK: jialc $5, 256
 0x00 0x01 0x05 0xd8 # CHECK: jic $5, 256
 0x00 0x00 0x1b 0xd8 # CHECK: jrc $27
 0x09 0x04 0x80 0x00 # CHECK: jr.hb $4
 0x43 0x0d 0xc8 0x49 # CHECK: ldc2 $8, -701($1)

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt

 0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4
 0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4
 0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23
 0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x40 0x08 0x80 0x03 # CHECK: mfc0 $8, $16, 3
 0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
 0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0
+0x41 0x60 0x00 0x24 # CHECK: dvp $zero
+0x41 0x60 0x00 0x04 # CHECK: evp $zero
 0x41 0x60 0x60 0x00 # CHECK: di
 0x41 0x60 0x60 0x20 # CHECK: ei
 0x41 0x6e 0x60 0x20 # CHECK: ei $14
+0x41 0x70 0x00 0x04 # CHECK: evp $16
+0x41 0x71 0x00 0x24 # CHECK: dvp $17
 0x41 0x7e 0x60 0x00 # CHECK: di $fp
 # FIXME: The encode/decode functions are not inverses of each other.
 #        The immediate should be 4 but the disassembler currently emits 8
 0x45 0x20 0x00 0x01 # CHECK: bc1eqz $f0, 8
 # FIXME: The encode/decode functions are not inverses of each other.
 #        The immediate should be 4 but the disassembler currently emits 8
 0x45 0x3f 0x00 0x01 # CHECK: bc1eqz $f31, 8
 # FIXME: The encode/decode functions are not inverses of each other.

test/MC/Mips/mips32r6/invalid.s

local_label:
         beqzc $2, 4194304        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
         beqzc $2, 4194303        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
         bnezc $2, -4194308       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
         bnezc $2, -4194303       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
         bnezc $2, 4194304        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
         bnezc $2, 4194303        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
         cache -1, 255($7)    # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
         cache 32, 255($7)    # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+        dvp $17, $3          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        dvp $17, 3           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        dvp 3                # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        evp $16, $3          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        evp $16, 3           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        evp 3                # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         jalr.hb $31          # CHECK: :[[@LINE]]:9: error: source and destination must be different
         jalr.hb $31, $31     # CHECK: :[[@LINE]]:9: error: source and destination must be different
         ldc2 $20, -1025($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
         ldc2 $20, 1024($s2)  # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
         lsa $2, $3, $4, 0    # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4
         lsa $2, $3, $4, 5    # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4
         pref -1, 255($7)     # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
         pref 32, 255($7)     # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate

test/MC/Mips/mips32r6/valid.s

a:
         cmp.sle.s  $f2,$f3,$f4      # CHECK: cmp.sle.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x8e]
         cmp.sle.d  $f2,$f3,$f4      # CHECK: cmp.sle.d $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x8e]
         cmp.sule.s $f2,$f3,$f4      # CHECK: cmp.sule.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8f]
         cmp.sule.d $f2,$f3,$f4      # CHECK: cmp.sule.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8f]
         di      $s8              # CHECK: di  $fp          # encoding: [0x41,0x7e,0x60,0x00]
         di                       # CHECK: di               # encoding: [0x41,0x60,0x60,0x00]
         div     $2,$3,$4         # CHECK: div $2, $3, $4   # encoding: [0x00,0x64,0x10,0x9a]
         divu    $2,$3,$4         # CHECK: divu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9b]
+        dvp     $4               # CHECK: dvp $4           # encoding: [0x41,0x64,0x00,0x24]
         ei      $14              # CHECK: ei  $14          # encoding: [0x41,0x6e,0x60,0x20]
         ei                       # CHECK: ei               # encoding: [0x41,0x60,0x60,0x20]
         eret
         eretnc                   # CHECK: eretnc           # encoding: [0x42,0x00,0x00,0x58]
+        evp     $5               # CHECK: evp $5           # encoding: [0x41,0x65,0x00,0x04]
         jialc   $5, 256          # CHECK: jialc $5, 256    # encoding: [0xf8,0x05,0x01,0x00]
         jic     $5, 256          # CHECK: jic $5, 256      # encoding: [0xd8,0x05,0x01,0x00]
         l.s     $f2, 8($3)       # CHECK: lwc1 $f2, 8($3)  # encoding: [0xc4,0x62,0x00,0x08]
         l.d     $f2, 8($3)       # CHECK: ldc1 $f2, 8($3)  # encoding: [0xd4,0x62,0x00,0x08]
         lsa     $2, $3, $4, 3    # CHECK: lsa  $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0x85]
         lwpc    $2,268           # CHECK: lwpc $2, 268     # encoding: [0xec,0x48,0x00,0x43]
         lwupc   $2,268           # CHECK: lwupc $2, 268    # encoding: [0xec,0x50,0x00,0x43]
         mfc0    $8,$15,1         # CHECK: mfc0 $8, $15, 1  # encoding: [0x40,0x08,0x78,0x01]

test/MC/Mips/mips64r6/invalid.s

.set noat
         cache -1, 255($7)    # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
         cache 32, 255($7)    # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
         dalign  $4, $2, $3, -1    # CHECK: :[[@LINE]]:29: error: expected 3-bit unsigned immediate
         dalign  $4, $2, $3, 8     # CHECK: :[[@LINE]]:29: error: expected 3-bit unsigned immediate
         dlsa    $2, $3, $4, 0     # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4
         dlsa    $2, $3, $4, 5     # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4
         drotr32 $2, $3, -1   # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
         drotr32 $2, $3, 32   # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
+        dvp $17, $3          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        dvp $17, 3           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        dvp 3                # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        evp $16, $3          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        evp $16, 3           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        evp 3                # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         jalr.hb $31          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
         jalr.hb $31, $31     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
         lsa     $2, $3, $4, 0     # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4
         lsa     $2, $3, $4, 5     # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4
         pref -1, 255($7)     # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
         pref 32, 255($7)     # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
         dmtc0  $4, $3, -1    # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
         dmtc0  $4, $3, 8     # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate

test/MC/Mips/mips64r6/valid.s

a:
         dmuhu   $2,$3,$4         # CHECK: dmuhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdd]
         dmul    $2,$3,$4         # CHECK: dmul $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9c]
         dmulu   $2,$3,$4         # CHECK: dmulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9d]
         dneg      $2                   # CHECK: dneg $2, $2                 # encoding: [0x00,0x02,0x10,0x2e]
         dneg      $2,$3                # CHECK: dneg $2, $3                 # encoding: [0x00,0x03,0x10,0x2e]
         dnegu     $2,$3                # CHECK: dnegu $2, $3                # encoding: [0x00,0x03,0x10,0x2f]
         dsubu   $14,-4586        # CHECK: daddiu $14, $14, 4586  # encoding: [0x65,0xce,0x11,0xea]
         dsubu   $15,$11,5025     # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
+        dvp     $4               # CHECK: dvp $4           # encoding: [0x41,0x64,0x00,0x24]
         ei                       # CHECK: ei               # encoding: [0x41,0x60,0x60,0x20]
         ei      $14              # CHECK: ei  $14          # encoding: [0x41,0x6e,0x60,0x20]
         eretnc                   # CHECK: eretnc                 # encoding: [0x42,0x00,0x00,0x58]
+        evp     $5               # CHECK: evp $5           # encoding: [0x41,0x65,0x00,0x04]
         j       1f               # CHECK: j $tmp0                # encoding: [0b000010AA,A,A,A]
                                  # CHECK:                        #   fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
         j       a                # CHECK: j a                    # encoding: [0b000010AA,A,A,A]
                                  # CHECK:                        #   fixup A - offset: 0, value: a, kind: fixup_Mips_26
         j       1328             # CHECK: j 1328                 # encoding: [0x08,0x00,0x01,0x4c]
         jal     21100            # CHECK: jal 21100              # encoding: [0x0c,0x00,0x14,0x9b]
         jr.hb   $4               # CHECK: jr.hb $4               # encoding: [0x00,0x80,0x04,0x09]
         jr      $ra              # CHECK: jr $ra                 # encoding: [0x03,0xe0,0x00,0x09]