AMDGPU: Try to commute when selecting s_addk_i32/s_mulk_i32

[• tstellarAMD]

LGTM.

[arsenm]

r280972

lib/Target/AMDGPU/SIShrinkInstructions.cpp

for (I = MBB.begin(); I != MBB.end(); I = Next) {
 
       // FIXME: We also need to consider movs of constant operands since
       // immediate operands are not folded if they have more than one use, and
       // the operand folding pass is unaware if the immediate will be free since
       // it won't know if the src == dest constraint will end up being
       // satisfied.
       if (MI.getOpcode() == AMDGPU::S_ADD_I32 ||
           MI.getOpcode() == AMDGPU::S_MUL_I32) {
-        const MachineOperand &Dest = MI.getOperand(0);
-        const MachineOperand &Src0 = MI.getOperand(1);
-        const MachineOperand &Src1 = MI.getOperand(2);
+        const MachineOperand *Dest = &MI.getOperand(0);
+        MachineOperand *Src0 = &MI.getOperand(1);
+        MachineOperand *Src1 = &MI.getOperand(2);
+
+        if (!Src0->isReg() && Src1->isReg()) {
+          if (TII->commuteInstruction(MI, false, 1, 2))
+            std::swap(Src0, Src1);
+        }
 
         // FIXME: This could work better if hints worked with subregisters. If
         // we have a vector add of a constant, we usually don't get the correct
         // allocation due to the subregister usage.
-        if (TargetRegisterInfo::isVirtualRegister(Dest.getReg()) &&
-            Src0.isReg()) {
-          MRI.setRegAllocationHint(Dest.getReg(), 0, Src0.getReg());
-          MRI.setRegAllocationHint(Src0.getReg(), 0, Dest.getReg());
+        if (TargetRegisterInfo::isVirtualRegister(Dest->getReg()) &&
+            Src0->isReg()) {
+          MRI.setRegAllocationHint(Dest->getReg(), 0, Src0->getReg());
+          MRI.setRegAllocationHint(Src0->getReg(), 0, Dest->getReg());
           continue;
         }
 
-        if (Src0.isReg() && Src0.getReg() == Dest.getReg()) {
-          if (Src1.isImm() && isKImmOperand(TII, Src1)) {
+        if (Src0->isReg() && Src0->getReg() == Dest->getReg()) {
+          if (Src1->isImm() && isKImmOperand(TII, *Src1)) {
             unsigned Opc = (MI.getOpcode() == AMDGPU::S_ADD_I32) ?
               AMDGPU::S_ADDK_I32 : AMDGPU::S_MULK_I32;
 
             MI.setDesc(TII->get(Opc));
             MI.tieOperands(0, 1);
           }
         }
       }

test/CodeGen/AMDGPU/s_addk_i32.ll

 ; SI-LABEL: {{^}}no_s_addk_i32_k0:
 ; SI: s_add_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x8000{{$}}
 ; SI: s_endpgm
 define void @no_s_addk_i32_k0(i32 addrspace(1)* %out, i32 %b) {
   %add = add i32 %b, 32768 ; 1 << 15
   store i32 %add, i32 addrspace(1)* %out
   ret void
 }
+
+@lds = addrspace(3) global [512 x i32] undef, align 4
+
+; SI-LABEL: {{^}}commute_s_addk_i32:
+; SI: s_addk_i32 s{{[0-9]+}}, 0x800{{$}}
+define void @commute_s_addk_i32(i32 addrspace(1)* %out, i32 %b) #0 {
+  %size = call i32 @llvm.amdgcn.groupstaticsize()
+  %add = add i32 %size, %b
+  call void asm sideeffect "; foo $0, $1", "v,s"([512 x i32] addrspace(3)* @lds, i32 %add)
+  ret void
+}
+
+declare i32 @llvm.amdgcn.groupstaticsize() #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }

test/CodeGen/AMDGPU/s_mulk_i32.ll

 ; SI-LABEL: {{^}}no_s_mulk_i32_k0:
 ; SI: s_mul_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x8001{{$}}
 ; SI: s_endpgm
 define void @no_s_mulk_i32_k0(i32 addrspace(1)* %out, i32 %b) {
   %mul = mul i32 %b, 32769 ; 1 << 15 + 1
   store i32 %mul, i32 addrspace(1)* %out
   ret void
 }
+
+@lds = addrspace(3) global [512 x i32] undef, align 4
+
+; SI-LABEL: {{^}}commute_s_mulk_i32:
+; SI: s_mulk_i32 s{{[0-9]+}}, 0x800{{$}}
+define void @commute_s_mulk_i32(i32 addrspace(1)* %out, i32 %b) #0 {
+  %size = call i32 @llvm.amdgcn.groupstaticsize()
+  %add = mul i32 %size, %b
+  call void asm sideeffect "; foo $0, $1", "v,s"([512 x i32] addrspace(3)* @lds, i32 %add)
+  ret void
+}
+
+declare i32 @llvm.amdgcn.groupstaticsize() #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }