AMDGPU: Make some scalar instructions commutable

[• tstellarAMD]

LGTM.

[arsenm]

r280784

lib/Target/AMDGPU/SOPInstructions.td

 def S_ADDC_U32 : SOP2_32 <"s_addc_u32",
   [(set i32:$sdst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
 } // End isCommutable = 1
 
 def S_SUBB_U32 : SOP2_32 <"s_subb_u32",
   [(set i32:$sdst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
 } // End Uses = [SCC]
 
+
+let isCommutable = 1 in {
 def S_MIN_I32 : SOP2_32 <"s_min_i32",
   [(set i32:$sdst, (smin i32:$src0, i32:$src1))]
 >;
 def S_MIN_U32 : SOP2_32 <"s_min_u32",
   [(set i32:$sdst, (umin i32:$src0, i32:$src1))]
 >;
 def S_MAX_I32 : SOP2_32 <"s_max_i32",
   [(set i32:$sdst, (smax i32:$src0, i32:$src1))]
 >;
 def S_MAX_U32 : SOP2_32 <"s_max_u32",
   [(set i32:$sdst, (umax i32:$src0, i32:$src1))]
 >;
+} // End isCommutable = 1
 } // End Defs = [SCC]
 
 
 let Uses = [SCC] in {
   def S_CSELECT_B32 : SOP2_32 <"s_cselect_b32">;
   def S_CSELECT_B64 : SOP2_64 <"s_cselect_b64">;
 } // End Uses = [SCC]
 
 let Defs = [SCC] in {
+let isCommutable = 1 in {
 def S_AND_B32 : SOP2_32 <"s_and_b32",
   [(set i32:$sdst, (and i32:$src0, i32:$src1))]
 >;
 
 def S_AND_B64 : SOP2_64 <"s_and_b64",
   [(set i64:$sdst, (and i64:$src0, i64:$src1))]
 >;
 
 def S_OR_B32 : SOP2_32 <"s_or_b32",
   [(set i32:$sdst, (or i32:$src0, i32:$src1))]
 >;
 
 def S_OR_B64 : SOP2_64 <"s_or_b64",
   [(set i64:$sdst, (or i64:$src0, i64:$src1))]
 >;
 
 def S_XOR_B32 : SOP2_32 <"s_xor_b32",
   [(set i32:$sdst, (xor i32:$src0, i32:$src1))]
 >;
 
 def S_XOR_B64 : SOP2_64 <"s_xor_b64",
   [(set i64:$sdst, (xor i64:$src0, i64:$src1))]
 >;
+} // End isCommutable = 1
+
 def S_ANDN2_B32 : SOP2_32 <"s_andn2_b32">;
 def S_ANDN2_B64 : SOP2_64 <"s_andn2_b64">;
 def S_ORN2_B32 : SOP2_32 <"s_orn2_b32">;
 def S_ORN2_B64 : SOP2_64 <"s_orn2_b64">;
 def S_NAND_B32 : SOP2_32 <"s_nand_b32">;
 def S_NAND_B64 : SOP2_64 <"s_nand_b64">;
 def S_NOR_B32 : SOP2_32 <"s_nor_b32">;
 def S_NOR_B64 : SOP2_64 <"s_nor_b64">;
def S_ASHR_I64 : SOP2_64_32 <"s_ashr_i64",
   [(set i64:$sdst, (sra i64:$src0, i32:$src1))]
 >;
 } // End Defs = [SCC]
 
 def S_BFM_B32 : SOP2_32 <"s_bfm_b32",
   [(set i32:$sdst, (AMDGPUbfm i32:$src0, i32:$src1))]>;
 def S_BFM_B64 : SOP2_64_32_32 <"s_bfm_b64">;
 def S_MUL_I32 : SOP2_32 <"s_mul_i32",
-  [(set i32:$sdst, (mul i32:$src0, i32:$src1))]
->;
+  [(set i32:$sdst, (mul i32:$src0, i32:$src1))]> {
+  let isCommutable = 1;
+}
 
 } // End AddedComplexity = 1
 
 let Defs = [SCC] in {
 def S_BFE_U32 : SOP2_32 <"s_bfe_u32">;
 def S_BFE_I32 : SOP2_32 <"s_bfe_i32">;
 def S_BFE_U64 : SOP2_64_32 <"s_bfe_u64">;
 def S_BFE_I64 : SOP2_64_32 <"s_bfe_i64">;

 def S_ADDK_I32_vi          : SOPK_Real_vi <0x0E, S_ADDK_I32>;
 def S_MULK_I32_vi          : SOPK_Real_vi <0x0F, S_MULK_I32>;
 def S_CBRANCH_I_FORK_vi    : SOPK_Real_vi <0x10, S_CBRANCH_I_FORK>;
 def S_GETREG_B32_vi        : SOPK_Real_vi <0x11, S_GETREG_B32>;
 def S_SETREG_B32_vi        : SOPK_Real_vi <0x12, S_SETREG_B32>;
 //def S_GETREG_REGRD_B32_vi  : SOPK_Real_vi <0x13, S_GETREG_REGRD_B32>; // see pseudo for comments
 def S_SETREG_IMM32_B32_vi  : SOPK_Real64<0x14, S_SETREG_IMM32_B32>,
                              Select_vi<S_SETREG_IMM32_B32.Mnemonic>;
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