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[AVX512] Fix zext + bitcast lowering pattern.
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Authored by igorb on Aug 28 2016, 11:26 PM.

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Summary

[AVX512] Fix v8i1 /v16i1 zext + bitcast lowering pattern. Explicitly zero upper bits.
Previous implementation generate incorrect code, for example

        t86: v8i1 = X86ISD::CVT2MASK t44
    t88: i8 = bitcast t86
t59: i32 = zero_extend t88    	

      t99: i8 = COPY_TO_REGCLASS t86, TargetConstant:i32<0>
 t59: i32 = SUBREG_TO_REG TargetConstant:i64<0>, t99, TargetConstant:i32<1>

  kmovb	%k0, %r10d

movb %r10b, %dil -> DI upper bits doesn't zero zeroed

Diff Detail

Repository
rL LLVM

Event Timeline

igorb updated this revision to Diff 69531.Aug 28 2016, 11:26 PM
igorb retitled this revision from to [AVX512] Fix zext + bitcast lowering pattern..
igorb updated this object.
igorb added a reviewer: delena.
igorb set the repository for this revision to rL LLVM.
igorb added a subscriber: llvm-commits.
igorb updated this revision to Diff 69846.Aug 31 2016, 6:55 AM
igorb added reviewers: guyblank, m_zuckerman.
delena accepted this revision.Sep 5 2016, 12:10 AM
delena edited edge metadata.
This revision is now accepted and ready to land.Sep 5 2016, 12:10 AM
This revision was automatically updated to reflect the committed changes.